公开(公告)号：GB2575933B

公开(公告)日：2021-09-29

申请号：GB201915589

申请日：2018-04-13

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  ZHENG XU ,  ZHENXING BI

IPC: H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated chips include a first semiconductor device and a second semiconductor device. The first semiconductor device includes a semiconductor channel, a first-type work function layer formed from a first material on the semiconductor channel, and a second-type work function layer formed from a second material on the first-type work function later layer. The second semiconductor device includes a semiconductor channel, a second-type work function layer formed the second material on the semiconductor channel, and a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.

公开(公告)号：GB2575933A

公开(公告)日：2020-01-29

申请号：GB201915589

申请日：2018-04-13

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  ZHENG XU ,  ZHENXING BI

IPC: H01L21/336

Abstract: Semiconductor devices and methods of forming the same include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.

公开(公告)号：GB2575598A

公开(公告)日：2020-01-15

申请号：GB201915742

申请日：2018-04-19

Applicant: IBM

Inventor： SHOGO MOCHIZUKI ,  CHOONGHYUN LEE ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

公开(公告)号：GB2616573B

公开(公告)日：2025-02-19

申请号：GB202309314

申请日：2021-10-21

Applicant: IBM

Inventor： YOUNGSEOK KIM ,  CHOONGHYUN LEE ,  TIMOTHY MATHEW PHILIP ,  SOON-CHEON SEO ,  INJO OK ,  ALEXANDER REZNICEK

IPC: G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

Abstract: A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

公开(公告)号：GB2604518A

公开(公告)日：2022-09-07

申请号：GB202207339

申请日：2020-10-12

Applicant: IBM

Inventor： CHANRO PARK ,  CHENG KANGGUO ,  RUILONG XIE ,  CHOONGHYUN LEE

IPC: H01L27/105

Abstract: A semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The method includes forming a sacrificial layer over a transistor drain contact; forming a first dielectric layer over the sacrificial layer; forming a cell contact hole through the first dielectric layer; forming an access contact hole through the first dielectric layer and exposing the sacrificial layer; removing the sacrificial layer thereby forming a cavity connecting a bottom opening of the cell contact hole and a bottom opening of the access contact hole; forming by atomic layer deposition in the cell contact hole a second dielectric layer including a seam; forming a bottom electrode within the cavity and in contact with the drain contact, the second dielectric layer, and the seam; and forming a top electrode over the first dielectric layer and in contact with the second dielectric layer and the seam.

公开(公告)号：GB2581116A

公开(公告)日：2020-08-05

申请号：GB202008885

申请日：2018-12-14

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.