公开(公告)号：DE60335981D1

公开(公告)日：2011-03-24

申请号：DE60335981

申请日：2003-03-19

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FRIED DAVID M ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/786

公开(公告)号：DE602004015793D1

公开(公告)日：2008-09-25

申请号：DE602004015793

申请日：2004-06-30

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L29/06 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

公开(公告)号：DE112012000717B4

公开(公告)日：2016-02-11

申请号：DE112012000717

申请日：2012-01-18

Applicant: IBM

Inventor： SHI YUN ,  CLARK WILLIAM F

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/84

Abstract: Halbleitereinheit, die aufweist: eine n-Wanne innerhalb einer p-Wanne in einer Siliciumschicht, wobei die Siliciumschicht oben auf einer vergrabenen Oxidschicht eines Silicium-auf-Isolator(SOI)-Substrats angeordnet ist; einen ersten Source-Bereich und einen zweiten Source-Bereich innerhalb eines Teils der p-Wanne; einen ersten Drain-Bereich und einen zweiten Drain-Bereich innerhalb eines Teils der p-Wanne und innerhalb eines Teils der n-Wanne; und ein Gate, das oben auf der n-Wanne angeordnet ist, wobei zwischen der n-Wanne und der p-Wanne ein Bereich mit einem lateralen hohen Feld erzeugt wird und zwischen dem Gate und der n-Wanne ein Bereich mit einem vertikalen hohen Feld erzeugt wird.

公开(公告)号：AU2003223306A8

公开(公告)日：2003-10-08

申请号：AU2003223306

申请日：2003-03-19

Applicant: IBM

Inventor： NOWAK EDWARD J ,  CLARK WILLIAM F ,  LANZEROTTI LOUIS D ,  FRIED DAVID M

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786 ,  H01L29/78 ,  H01L33/00

Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

公开(公告)号：MY115263A

公开(公告)日：2003-04-30

申请号：MYPI9802513

申请日：1998-06-05

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FERENCE THOMAS G ,  HOOK TERENCE B ,  MARTIN DALE W

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/78 ,  H01L21/285 ,  H01L21/30 ,  H01L21/316 ,  H01L21/318 ,  H01L21/324

Abstract: METHOD OF FORMING A FILM (14, 15, 16, 18, 19; 24, 25, 26, 28, 29; 34, 35,36, 38A, 38B, 39) FOR A SEMICONDUCTOR DEVICE (100, 200, 300) IN WHICH A SOURCE MATERIAL COMPRISING A DEUTERATES SPECIES IS PROVIDED DURING FORMATION OF THE FILM.

公开(公告)号：HK1026064A1

公开(公告)日：2000-12-01

申请号：HK00105169

申请日：2000-08-17

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  NOWAK EDWARD J ,  PRICER WILBUR D ,  TONG MINH H

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L

Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.