公开(公告)号：WO2006088533A3

公开(公告)日：2007-09-27

申请号：PCT/US2005043464

申请日：2005-12-02

Applicant: IBM ,  ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

Inventor： ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

IPC: B23H3/00

CPC classification number: C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

Abstract: Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

Abstract translation: 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：JP2011014904A

公开(公告)日：2011-01-20

申请号：JP2010142938

申请日：2010-06-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YANG CHIH-CHAO ,  THEODORUS EDUARDUS STANDAERT ,  EDELSTEIN DANIEL C

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an interconnect structure including a gouging feature at the bottom of a via opening, and to provide a method of fabricating the same.SOLUTION: The method does not disrupt the coverage of the deposited trench diffusion barrier in a line opening that is located atop the via opening, and/or does not introduce damages caused by creating a gouging feature at the bottom of the via opening by sputtering into the interconnect dielectric material that includes the via and line openings. Such an interconnect structure is achieved by providing a gouging feature in the bottom of the via opening by first forming the line opening within the interconnect dielectric, followed by forming the via opening and then the gouging feature.

Abstract translation: 要解决的问题：提供一种在通孔开口的底部包括刨花特征的互连结构，并提供其制造方法。解决方案：该方法不会破坏线中沉积的沟槽扩散阻挡层的覆盖 位于通孔开口顶部的开口，和/或不引入由通过溅射在通孔开口的底部通过包括通孔和线路开口的互连电介质材料产生气流特征而造成的损害。 通过在互连电介质中首先形成线路开口，然后形成通孔开口，然后形成沟槽特征，在通孔开口的底部提供气泡特征来实现这种互连结构。

公开(公告)号：JP2010283347A

公开(公告)日：2010-12-16

申请号：JP2010123865

申请日：2010-05-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOGAMI TAKESHI ,  EDELSTEIN DANIEL C ,  ROSSNAGEL STEPHEN M ,  FLAITZ PHILIP LEE ,  DEHAVEN PATRICK WILLIAM ,  YANG CHIH-CHAO

IPC: H01L21/3205 ,  H01L21/28 ,  H01L23/52

CPC classification number: H01L21/2855 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  Y10T428/24917

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of attaining high reliability and a high production yield by eliminating a void generation portion in a liner/copper interface. SOLUTION: The method of forming a diffusion barrier used for manufacturing the semiconductor device includes a step for depositing an iridium-doped tantalum-based barrier layer on a pattern-formed intermediate dielectric (ILD) layer by a physical vapor deposition (PVD) process, and the barrier layer is deposited to form the barrier layer into amorphous structure as a result, at least 60% of an iridium concentration in terms of atomic weight. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过消除衬里/铜界面中的空隙生成部分来制造能够获得高可靠性和高生产率的半导体器件的方法。 解决方案：形成用于制造半导体器件的扩散阻挡层的方法包括通过物理气相沉积（PVD）在形成图案的中间电介质（ILD）层上沉积铱掺杂的钽基阻挡层的步骤 ），并且阻挡层被沉积以形成无定形结构的阻挡层，至少60％的铱浓度以原子量计。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008277807A

公开(公告)日：2008-11-13

申请号：JP2008102183

申请日：2008-04-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  EDELSTEIN DANIEL C ,  BREYTA GREGORY ,  COLBURN MATTHEW EARL ,  SHOM PONOTH

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces cross-talk between conducting lines for wiring. SOLUTION: A method of forming a cavity in a semiconductor device 300 comprises a step for depositing an anti-nucleating layer 318 on the interior surface of the cavity in an ILD layer of the semiconductor device. This anti-nucleating layer prevents a subsequently-deposited dielectric layer from being formed in the cavity. By preventing the formation of these layers, capacitance is reduced, thereby resulting in improved semiconductor performance. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种减少用于布线的导线之间的串扰的半导体器件。 解决方案：在半导体器件300中形成腔的方法包括在半导体器件的ILD层中的空腔的内表面上沉积抗成核层318的步​​骤。 该防成核层防止在空腔中形成随后沉积的介电层。 通过防止这些层的形成，电容降低，从而提高半导体性能。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2005217419A

公开(公告)日：2005-08-11

申请号：JP2005021309

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  ANDRICACOS PANAYOTIS C ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  MAGERLEIN JOHN H ,  PETRARCA KEVIN S ,  STEIN KENNETH JAY ,  VOLANT RICHARD P

IPC: H01F41/04 ,  H01F17/00 ,  H01L21/02 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/08

CPC classification number: H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an inductor and a method of forming the inductor. SOLUTION: The method of forming the inductor comprises (a) a step for providing a semiconductor substrate, (b) a step for forming a dielectric layer on the surface of the substrate, (c) a step for forming a lower trench in the dielectric layer, (d) a step for forming a resist layer on the surface of the dielectric layer, (e) a step for forming an upper trench which is aligned to the lower trench and whose bottom is opened for the lower trench in the resist layer, and (f) a step for completely filling the lower trench with a conductor and at least partially filling the upper trench with the conductor to form the inductor. The semiconductor structure includes the inductor including the upper surface, bottom surface and sidewall and a means that allows the inductor to be electrically contacted, the lower section of the inductor is extended by a distance that the lower section of the inductor is fixed in the dielectric layer formed on the substrate, and the upper section thereof is extended on the dielectric layer. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供电感器和形成电感器的方法。 形成电感器的方法包括（a）提供半导体衬底的步骤，（b）在衬底的表面上形成电介质层的步骤，（c）形成下沟槽的步骤 在电介质层中，（d）在电介质层的表面上形成抗蚀剂层的步骤，（e）形成上沟槽的步骤，该上沟槽与下沟槽对准并且底部为下沟槽开口 抗蚀剂层，和（f）用导体完全填充下沟槽并且至少部分地用导体填充上沟槽以形成电感器的步骤。 半导体结构包括电感器，其包括上表面，底表面和侧壁，以及允许电感器电接触的装置，电感器的下部延伸一段距离，电感器的下部固定在电介质中 层，其上部在电介质层上延伸。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：DE112010003269B4

公开(公告)日：2014-05-15

申请号：DE112010003269

申请日：2010-08-04

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  EDELSTEIN DANIEL C ,  KOESTER STEVEN ,  SOLOMAN PAUL M ,  HINSBERG WILLIAM D ,  KIM HO-CHEOL

IPC: H01L23/535 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

Abstract: Struktur, umfassend: eine erste Vielzahl von leitfähigen Linien, die einen ersten Rasterabstand aufweist und in wenigstens einer dielektrischen Schicht eingebettet ist, wobei jede aus der ersten Vielzahl von leitfähigen Linien ein Paar von Seitenwänden aufweist, die parallel zu einer ersten Vertikalebene sind, und eine Endwand, die dem Paar von Seitenwänden direkt angrenzt und in einer zweiten Vertikalebene liegt, wobei der Winkel zwischen der ersten Vertikalebene und der zweiten Vertikalebene weniger als 45 Grad beträgt; und eine Vielzahl von leitfähigen Durchkontaktierungen, wobei jede aus der Vielzahl von leitfähigen Durchkontaktierungen einen Endabschnitt von einer aus der Vielzahl von leitfähigen Linien kontaktiert und in der wenigstens einen dielektrischen Schicht eingebettet ist, und wobei die zweite Vertikalebene jede aus der Vielzahl von leitfähigen Durchkontaktierungen schneidet und ein Abschnitt von jeder aus der Vielzahl von leitfähigen Durchkontaktierungen auf einer Seite der zweiten Vertikalebene vorhanden ist und ein anderer Abschnitt von jeder aus der Vielzahl von leitfähigen Durchkontaktierungen auf der anderen Seite der zweiten Vertikalebene vorhanden ist.

公开(公告)号：GB2365622B

公开(公告)日：2004-08-11

申请号：GB0103577

申请日：2001-02-14

Applicant: IBM

Inventor： SAMBUCETTI CARLOS J ,  EDELSTEIN DANIEL C ,  GAUDIELLO JOHN G ,  RUBINO JUDITH M ,  WALKER GEORGE

IPC: H05K3/34 ,  C23C18/16 ,  H01L21/60 ,  H01L23/12 ,  H01L23/485 ,  H01L23/532 ,  H05K3/24 ,  H05K13/06

Abstract: A method for preparing a copper pad surface for electrical connection that has superior diffusion barrier and adhesion properties is provided. In the method, a copper pad surface is first provided that has been cleaned by an acid solution, a protection layer of a phosphorus or boron-containing metal alloy is then deposited on the copper pad surface, and then an adhesion layer of a noble metal is deposited on top of the protection layer. The protection layer may be a single layer, or two or more layers intimately joined together formed of a phosphorus or boron-containing metal alloy such as Ni-P, Co-P, Co-W-P, Co-Sn-P, Ni-W-P, Co-B, Ni-B, Co-Sn-B, Co-W-B and Ni-W-B to a thickness between about 1,000 Å and about 10,000 Å. The adhesion layer can be formed of a noble metal such as Au, Pt, Pd and Ag to a thickness between about 500 Å and about 4,000 Å.

公开(公告)号：GB2504418A

公开(公告)日：2014-01-29

申请号：GB201319175

申请日：2012-04-04

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  GATES STEPHEN M ,  LI BAOZHEN ,  EDELSTEIN DANIEL C

IPC: H01L23/525

Abstract: An improved electrical-fuse (e-fuse) device (200) including a dielectric layer (102) having a first top surface (108), two conductive features (104, 106) embedded in the dielectric layer (102) and a fuse element (122). Each conductive feature (104, 106) has a second top surface (110, 112) and a metal cap (114, 116) directly on the second top surface (110, 112). Each metal cap (114, 116) has a third top surface (118, 120) that is above the first top surface (108) of the dielectric layer (102). The fuse element (122) is on the third top surface (118, 120) of each metal cap (114, 116) and on the first top surface (108) of the dielectric layer (102). A method of forming the e-fuse device (200) is also provided.

公开(公告)号：CA2368950C

公开(公告)日：2012-10-02

申请号：CA2368950

申请日：2000-05-15

Applicant: IBM

Inventor： EDELSTEIN DANIEL C ,  MCGAHAY VINCENT ,  NYE HENRY A III ,  OTTEY BRIAN G R ,  PRICE WILLIAM H

IPC: H01L23/485 ,  H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/532

Abstract: A structure comprising a layer of copper (1), a barrier layer (10), a layer of AlCu (9), and a pad-limiting layer (7), wherein the layer of AlCu and barrier layer are interposed between the layer of copper and pad-limiting layer.

公开(公告)号：DE10236430A1

公开(公告)日：2003-02-27

申请号：DE10236430

申请日：2002-08-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CONTI RICHARD A ,  EDELSTEIN DANIEL C ,  LEE GILL YOUNG

IPC: C23C16/40 ,  H01L21/768 ,  H01L21/312 ,  H01L21/316 ,  H01L23/522

Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.