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    13.
    发明专利
    未知

    公开(公告)号：DE60133214T2

    公开(公告)日：2009-04-23

    申请号：DE60133214

    申请日：2001-11-13

    Applicant: IBM ,  QIMONDA AG

    Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

    IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

    Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

    14.
    发明专利
    未知

    公开(公告)号：AT490552T

    公开(公告)日：2010-12-15

    申请号：AT07822110

    申请日：2007-10-31

    Applicant: IBM

    Inventor： DAUBENSPECK TIMOTHY HARRISON ,  MUZZY CHRISTOPHER DAVID ,  GAMBINO JEFFREY PETER ,  SAUTER WOLFGANG

    IPC: H01L23/31 ,  H01L23/485

    Abstract: Methods of forming wire and solder bonds are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer; forming in a material a first opening to the silicon oxide layer over the wire bond metal region and a second opening exposing the solder bond metal region; forming the solder bond to the solder bond metal region while the wire bond metal region is covered; exposing the wire bond metal region including removing the silicon oxide layer to the wire bond metal region; and forming the wire bond to the wire bond metal region. Wire bonds and solder bonds can be made accessible on a single multi-part wafer (MPW) or on a single chip, if necessary, and can be formed substantially simultaneously.

    15.
    发明专利
    未知

    公开(公告)号：DE60133214D1

    公开(公告)日：2008-04-24

    申请号：DE60133214

    申请日：2001-11-13

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

    IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

    Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

    19.
    发明专利
    未知

    公开(公告)号：AT497419T

    公开(公告)日：2011-02-15

    申请号：AT07822113

    申请日：2007-10-31

    Applicant: IBM

    Inventor： DAUBENSPECK TIMOTHY HARRISON ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY PETER ,  MUZZY CHRISTOPHER DAVID

    IPC: B23K1/20 ,  B23K20/24 ,  H01L25/065

    Abstract: Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.

    20.
    发明专利
    未知

    公开(公告)号：DE69636808T2

    公开(公告)日：2007-11-08

    申请号：DE69636808

    申请日：1996-11-08

    Applicant: IBM

    Inventor： GAMBINO JEFFREY PETER ,  JASO MARK ANTHONY ,  NESBIT LARRY ALAN

    IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L21/304 ,  H01L21/321

    Abstract: Forming inter level studs of at least two different materials, in an insulating layer on a semiconductor wafer comprises: (a) forming a layer of insulating material on a semiconductor wafer; (b) planarising the insulating layer; (c) forming a first group of vias through the insulating layer; (d) forming a layer of first conducting material on the insulating layer; (e) forming a second group of vias through the first conducting material layer and insulating layer; (f) forming a layer of a second conductive material filling the first and second group of vias; (g) removing the second conductive layer to expose the first conductive material layer, such that the second conductive material remains only in the first and second via groups; and (h) removing the exposed first conductive material layer. Also claimed is the method as above in which steps (b),(h) and (i) are achieved by chemically-mechanically polishing, (c) and (e) are etched, and dopant is implanted into the wafer through the second group of vias and the wafer is annealed after (e).

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