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    Checking Arithmetic operations using residue modulo generation by applying the modulo operations of the prime factors of the checking value.
    12.
    发明专利
    Checking Arithmetic operations using residue modulo generation by applying the modulo operations of the prime factors of the checking value. 未知

    公开(公告)号：GB2456624A

    公开(公告)日：2009-07-22

    申请号：GB0822772

    申请日：2008-12-15

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  KROENER KLAUS MICHAEL ,  HAESS JUERGEN

    IPC: G06F11/00 ,  G06F7/72 ,  G06F11/10

    Abstract: Disclosed is a method and an apparatus using residue modulo checking for arithmetic operations. To get a high Modulo m and thus a high residue modulo checking coverage within a checking flow 31, at least two modulo operations 32, 33 are separately applied in parallel, a first Modulo q0 operation and at least one second Modulo qn operation, where q0, q1, q2,... qn-1, qn, are different primes with m=q0*q1*q2*. . .*qn-1*qn. The checking is done by comparing the residue modulo of the result of an arithmetic operation 36 with the results of the modulo operations on the inputs of the arithmetic operation 35. The modulo operations may be provided by a modulo decode for the modulos applied in the parallel flows or by providing a modulo shift table. The values of m may be 15 or 255 and the values of q may be 3 and 5 or 3, 5 and 17, respectfully.

    High availability, high precision system clock register arrangement
    14.
    发明专利
    High availability, high precision system clock register arrangement 未知

    公开(公告)号：GB2489307A

    公开(公告)日：2012-09-26

    申请号：GB201204158

    申请日：2012-03-09

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  ENGLER EBERHARD ,  BUTTLAR JOACHIM VON ,  MEISSNER KLAUS ,  LEHNERT FRANK

    IPC: G06F1/14 ,  G06F11/16

    Abstract: A time of day (TOD) system clock associated with a processing core (2) comprises a host clock register (5) incremented by means of a high precision oscillator (3) and a firmware clock register (6), incremented every time the host clock register (5) is incremented. The system monitors for failures of the host clock register (5), and during a failure of the host clock register (5) increments the firmware clock register (6) by means of timing signals of the processing core (2). Upon receiving a clock value read request providing the content of the host clock register (5) if no failure is detected and updating the firmware clock register (6) with the value of the host clock register (5).

    Controlling timeouts of an error recovery procedure in a digital circuit
    19.
    发明专利
    Controlling timeouts of an error recovery procedure in a digital circuit 未知

    公开(公告)号：GB2456656A

    公开(公告)日：2009-07-29

    申请号：GB0822778

    申请日：2008-12-15

    Applicant: IBM

    Inventor： MAYER ULRICH ,  LEHNERT FRANK ,  GERWIG GUENTER ,  SWANEY SCOTT BARNETT

    IPC: G06F11/07 ,  G06F9/38

    Abstract: The invention relates to apparatus for controlling timeouts and delays of an error recovery procedure in a digital circuit, e.g. a microprocessor. The apparatus comprises a finite state machine (FSM) 10, having a plurality of states 12 and a plurality of transitions 14. Transitions 14 are arranged between two states 12 respectively. States 12 correspond with operation steps (40, 44, 52, 56, 58, 64) of the error recovery procedure, including error classification, a drain operation, a fence operation in which a microprocessor core does not communicate with memory, a reset or refresh operation, and automatic built-in self test (ABIST). Transitions 14 of the FSM 10 depend on conditions (46, 50, 53, 57, 59, 62) for the error recovery procedure. The FSM 10 is coupled with a timeout logic circuit 20 which controls a timer to obtain the timeouts (46, 53, 57, 59) of the error recovery procedure. The FSM is configurable by a data vector which describes states 12 of the FSM for which the timer should be engaged.

    Residue calculation in modulo system using 4:2 counter
    20.
    发明专利
    Residue calculation in modulo system using 4:2 counter 未知

    公开(公告)号：GB2456406A

    公开(公告)日：2009-07-22

    申请号：GB0822762

    申请日：2008-12-15

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  FLEISCHER BRUCE MARTIN ,  HAESS JUERGEN ,  TRONG SON DAO ,  SCHWARZ ERIC MARK ,  WETTER HOLGER

    IPC: G06F7/72

    Abstract: A residue of an operand with a width of n bits with respect to a modulo m where m=2b-1, can be calculated by partitioning the operand into segments, each of b bits starting with the Least Significant Bit (LSB). The segments are applied to a counter reduction tree (21) comprising levels (22, 23) of adders (24) The adders (24) of a first level (22) below an operand register (25) with successive registers keeping the successive bit positions of the operand are 4:2 counters (24) having four inputs (In1, In2, In3, In4) plus a propagate input (44), a carry and a sum output (45, 46) plus a propagate output (43) each. the first level (22) are grouped in fours, such that the propagate outputs (43) are ring like connected with the propagate inputs (44), and that the first to fourth inputs (In1, In2, In3, In4) of the counters (24) are connected with successive registers of said operand register (25) such that first inputs (In4) of the counters (24) are connected with four successive registers in ascending order followed by second (In3), third (In2) and fourth inputs (In1), wherein a decoding is performed only one time at the end of the counter tree (21) and thus at the end of the residue generation process. This leads to a reduction in the area needed on the chip to make the calculation, relaxes the timing requirement, as the calculation requires fewer logical levels, and increases the error detection rate for a single random type of operation.

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