公开(公告)号：WO2005122245A2

公开(公告)日：2005-12-22

申请号：PCT/US2005018521

申请日：2005-05-26

Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L27/01 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer (102, 106) is formed above a lower conductor layer (100) and an upper conductor layer (104, 108) is formed above the dielectric layer. The invention then forms an etch stop layer (200) above the upper conductor layer and the dielectric layer, and forms a hardmask (202) (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist (300) is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Abstract translation: 公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。 在该方法中，在下导体层（100）的上方形成介电层（102,106），在电介质层的上方形成上导体层（104,108）。 然后，本发明在上导体层和电介质层之上形成蚀刻停止层（200），并在蚀刻停止层上形成硬掩模（202）（氧化硅硬掩模，氮化硅硬掩模等）。 接下来，在硬掩模上图案化光致抗蚀剂（300），其允许通过光刻胶蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

公开(公告)号：WO2012047458A2

公开(公告)日：2012-04-12

申请号：PCT/US2011051348

申请日：2011-09-13

Applicant: IBM ,  DEMUYNCK DAVID A ,  HE ZHONG-XIANG ,  MIGA DANIEL R ,  MOON MATTHEW D ,  VANSLETTE DANIEL S ,  WHITE ERIC J

Inventor： DEMUYNCK DAVID A ,  HE ZHONG-XIANG ,  MIGA DANIEL R ,  MOON MATTHEW D ,  VANSLETTE DANIEL S ,  WHITE ERIC J

IPC: H01L21/28

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC (10) includes at least one trench (20) within a dielectric layer (25) disposed on a substrate (30). The trench is conformally coated with a liner and seed layer (35), and includes an interconnect (40) within. The interconnect includes a hard mask (45) on the sidewalls of the interconnect.

Abstract translation: 本公开一般涉及集成电路（IC），IC互连及其制造方法，并且更具体地涉及高性能电感器。 IC（10）包括设置在衬底（30）上的电介质层（25）内的至少一个沟槽（20）。 沟槽共形涂覆有衬里和籽晶层（35），并且包括内部的互连（40）。 该互连包括互连侧壁上的硬掩模（45）。

公开(公告)号：WO2011162949A2

公开(公告)日：2011-12-29

申请号：PCT/US2011039560

申请日：2011-06-08

Applicant: IBM ,  DANG DINH ,  DOAN THAI ,  DUNBAR GEORGE A ,  HE ZHONG-XIANG ,  HERRIN RUSSELL T ,  JAHNES CHRISTOPHER V ,  MALING JEFFREY C ,  MURPHY WILLIAM J ,  STAMPER ANTHONY K ,  TWOMBLY JOHN G ,  WHITE ERIC J

Inventor： DANG DINH ,  DOAN THAI ,  DUNBAR GEORGE A ,  HE ZHONG-XIANG ,  HERRIN RUSSELL T ,  JAHNES CHRISTOPHER V ,  MALING JEFFREY C ,  MURPHY WILLIAM J ,  STAMPER ANTHONY K ,  TWOMBLY JOHN G ,  WHITE ERIC J

IPC: B81B3/00 ,  B81C1/00 ,  H01H59/00

CPC classification number: B81C1/00365 ,  B81B3/0021 ,  B81B3/0072 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity (60a, 60b) having a planar surface using a reverse damascene process.

Abstract translation: 提供了平面腔微机电系统（MEMS）结构，制造方法和设计结构。 该方法包括使用反向镶嵌工艺形成具有平面表面的至少一个微机电系统（MEMS）腔（60a，60b）。

公开(公告)号：WO2009140052A3

公开(公告)日：2010-01-21

申请号：PCT/US2009041861

申请日：2009-04-28

Applicant: IBM ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

Inventor： ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

IPC: H01L21/335

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Abstract translation: 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。

公开(公告)号：GB2494600B

公开(公告)日：2015-02-25

申请号：GB201300265

申请日：2011-06-08

Applicant: IBM

Inventor： DANG DINH ,  DOAN THAI ,  DUNBAR GEORGE A ,  HE ZHONG-XIANG ,  HERRIN RUSSELL T ,  JAHNES CHRISTOPHER V ,  MALING JEFFREY C ,  MURPHY WILLIAM J ,  STAMPER ANTHONY K ,  TWOMBLY JOHN G ,  WHITE ERIC J

IPC: B81B3/00 ,  B81C1/00 ,  H01H57/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is moveable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity.

公开(公告)号：GB2498154B

公开(公告)日：2014-05-07

申请号：GB201307079

申请日：2011-09-13

Applicant: IBM

Inventor： DEMUYNCK DAVID ,  HE ZHONG-XIANG ,  MIGA DANIEL ,  MOON MATTHEW D ,  VANSLETTE DANIEL ,  WHITE ERIC J

IPC: H01L21/768 ,  H01L23/522

公开(公告)号：GB2485693B

公开(公告)日：2014-05-28

申请号：GB201201195

申请日：2010-08-26

Applicant: IBM

Inventor： BOOTH ROGER A JR ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

公开(公告)号：GB2485693A

公开(公告)日：2012-05-23

申请号：GB201201195

申请日：2010-08-26

Applicant: IBM

Inventor： BOOTH ROGER A JR ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

公开(公告)号：DE112010003418T5

公开(公告)日：2012-08-23

申请号：DE112010003418

申请日：2010-08-26

Applicant: IBM

Inventor： BOOTH JR ROGER A ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG

IPC: H01L27/08 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52

Abstract: Eine verflochtene Struktur kann mindestens eine erste Metallleitung, mindestens eine zweite Metallleitung, die parallel zu der mindestens einen ersten Metallleitung verläuft und von der mindestens einen ersten Metallleitung getrennt ist, und eine dritte Metallleitung umfassen, die mit Enden der mindestens einen ersten Metallleitung in Kontakt steht und von der mindestens einen zweiten Metallleitung getrennt ist. Die mindestens eine erste Metallleitung steht vertikal mit keiner Metalldurchkontaktierung in Kontakt, und mindestens eine zweite Metallleitung kann vertikal mit mindestens einer Metalldurchkontaktierung in Kontakt stehen. Mehrere Schichten verflochtener Strukturen können vertikal gestapelt sein. Alternativ kann eine verflochtene Struktur mehrere erste Metallleitungen und mehrere zweite Metallleitungen umfassen, wobei keine Metallleitung vertikal mit einer Metalldurchkontaktierung in Kontakt steht. Mehrere Einheiten einer verflochtenen Struktur können sich seitlich wiederholen und einander benachbart sein, mit oder ohne Drehung, und/oder vertikal gestapelt sein, um einen Kondensator zu bilden.

公开(公告)号：DE112011102130B4

公开(公告)日：2019-03-14

申请号：DE112011102130

申请日：2011-06-08

Applicant: IBM

Inventor： DUNBAR GEORGE A ,  HE ZHONG-XIANG ,  MALING JEFFREY C ,  MURPHY WILLIAM J ,  STAMPER ANTHONY K

IPC: B81C1/00 ,  B81B7/00

Abstract: Verfahren zum Bilden mindestens eines mikroelektromechanischen Systems (MEMS), aufweisend:Bilden einer unteren Verdrahtungsschicht auf einem Substrat (10);Bilden mehrerer diskreter parallel zueinander verlaufender Leiter (14) aus der unteren Verdrahtungsschicht, wobei die parallel zueinander verlaufenden Leiter (14) an einem jeweiligen ersten Ende durch einen ersten Verbindungsleiter, der senkrecht zu den parallel zueinander verlaufende Leitern (14) verläuft, verbunden sind, und wobei Längen der parallel zueinander verlaufende Leiter (14) von einem außenliegenden der Leiter (14) der so geschlitzten Leiterstruktur zu einem anderen außenliegenden Leiter (14) der geschlitzten Leiterstruktur suksessive zunehmen,Bilden eines zweiten Verbindungsleiters, der die parallel zueinander verlaufenden Leiter (14) an einem jeweiligen zweiten Ende der parallel zueinander verlaufende Leiter (14) miteinander verbindet, und wobei der erste Verbindungsleiter und der zweite Verbindungsleiter jeweils eine Breite aufweist, die geringer ist als eine Breite eines der parallel zueinander verlaufenden Leiter (14), wobei eine untere Kondensatorplatte des MEMS durch die parallel zueinander verlaufenden Leiter (14) sowie den ersten und den zweiten Verbindungsleiter gebildet wird, undBilden eines MEMS-Elektrodenarms über den mehreren parallel zueinander verlaufender Leitern (14), wobei der MEMS-Elektrodenarm eine obere Kondensatorplatte des MEMS aufweist.