11.
    发明专利
    未知

    公开(公告)号:DE60034611T2

    公开(公告)日:2008-01-31

    申请号:DE60034611

    申请日:2000-02-04

    Applicant: QIMONDA AG IBM

    Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.

    14.
    发明专利
    未知

    公开(公告)号:AT470237T

    公开(公告)日:2010-06-15

    申请号:AT03796085

    申请日:2003-12-08

    Applicant: IBM

    Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

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