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公开(公告)号:DE60034611T2
公开(公告)日:2008-01-31
申请号:DE60034611
申请日:2000-02-04
Applicant: QIMONDA AG , IBM
Inventor: WEBER STEFAN J , IGGULDEN ROY , NARAYAN CHANDRASEKHAR , BRINTZINGER AXEL CHRISTOPH , HOINKIS MARK , VAN DEN BERG ROBERT
IPC: H01H85/00 , H01H69/02 , H01L23/525 , H01L21/82
Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.
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公开(公告)号:DE60141254D1
公开(公告)日:2010-03-25
申请号:DE60141254
申请日:2001-12-19
Applicant: INFINEON TECHNOLOGIES CORP , IBM
Inventor: BOETTCHER STEVEN H , HO HERBERT L , HOINKIS MARK , LEE HYUN KOO , WANG YUN-YU , WONG KWONG HON
IPC: C23C16/34 , H01L21/3205 , H01L21/44 , H01L21/768 , H01L23/52 , H01L23/532
Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.
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公开(公告)号:DE60332865D1
公开(公告)日:2010-07-15
申请号:DE60332865
申请日:2003-12-08
Applicant: IBM
Inventor: CLEVENGER LARRY , DALTON TIMOTHY , HOINKIS MARK , KALDOR STEFFEN , KUMAR KAUSHIK , LA TULIPE DOUGLAS JR , SEO SOON-CHEON , SIMON ANDREW , WANG YUN-YU , YANG CHIH-CHAO , YANG HAINING
IPC: H01L21/768
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公开(公告)号:AT470237T
公开(公告)日:2010-06-15
申请号:AT03796085
申请日:2003-12-08
Applicant: IBM
Inventor: CLEVENGER LARRY , DALTON TIMOTHY , HOINKIS MARK , KALDOR STEFFEN , KUMAR KAUSHIK , LA TULIPE DOUGLAS , SEO SOON-CHEON , SIMON ANDREW , WANG YUN-YU , YANG CHIH-CHAO , YANG HAINING
IPC: H01L21/768
Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
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公开(公告)号:DE102004028026B4
公开(公告)日:2006-08-10
申请号:DE102004028026
申请日:2004-06-09
Applicant: INFINEON TECHNOLOGIES AG , IBM
Inventor: KUMAR KAUSHIK , CLEVENGER LARRY , DALTON TIMOTHY J , LA TULIPE DOUGLAS C , COWLEY ANDY , KALTALIOGLU ERDEM , SCHACHT JOCHEN , HOINKIS MARK , SIMON ANDREW H , KALDOR STEFFEN , YANG CHIH-CHAO
IPC: H01L21/3213 , H01L21/033 , H01L21/311 , H01L21/768
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公开(公告)号:DE102004028026A1
公开(公告)日:2005-02-03
申请号:DE102004028026
申请日:2004-06-09
Applicant: INFINEON TECHNOLOGIES AG , IBM
Inventor: KUMAR KAUSHIK , CLEVENGER LARRY , DALTON TIMOTHY J , LA TULIPE DOUGLAS C , COWLEY ANDY , KALTALIOGLU ERDEM , SCHACHT JOCHEN , HOINKIS MARK , SIMON ANDREW H , KALDOR STEFFEN , YANG CHIH-CHAO
IPC: H01L21/033 , H01L21/311 , H01L21/768 , H01L21/3213
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公开(公告)号:AT457081T
公开(公告)日:2010-02-15
申请号:AT01988335
申请日:2001-12-19
Applicant: IBM , INFINEON TECHNOLOGIES CORP
Inventor: BOETTCHER STEVEN , HO HERBERT , HOINKIS MARK , LEE HYUN , WANG YUN-YU , WONG KWONG
IPC: C23C16/34 , H01L21/768 , H01L21/3205 , H01L23/52 , H01L23/532
Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.
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公开(公告)号:DE60034611D1
公开(公告)日:2007-06-14
申请号:DE60034611
申请日:2000-02-04
Applicant: IBM , INFINEON TECHNOLOGIES AG
Inventor: WEBER STEFAN J , IGGULDEN ROY , NARAYAN CHANDRASEKHAR , BRINTZINGER AXEL CHRISTOPH , HOINKIS MARK , VAN DEN BERG ROBERT
IPC: H01H85/00 , H01H69/02 , H01L23/525 , H01L21/82
Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.
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19.
公开(公告)号:AU2003298347A1
公开(公告)日:2004-06-30
申请号:AU2003298347
申请日:2003-12-08
Applicant: IBM
Inventor: CLEVENGER LARRY , DALTON TIMOTHY , HOINKIS MARK , KALDOR STEFFEN , KUMAR KAUSHIK , TULIPE DOUGLAS JR LA , SEO SOON-CHEON , SIMON ANDREW , WANG YUN-YU , YANG CHIH-CHAO , YANG HAINING
IPC: H01L21/768
Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
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公开(公告)号:AU2002241651A1
公开(公告)日:2002-07-24
申请号:AU2002241651
申请日:2001-12-19
Applicant: INFINEON TECHNOLOGIES CORP , IBM
Inventor: WONG KWONG HON , LEE HYUN KOO , WANG YUN-YU , HO HERBERT L , HOINKIS MARK , BOETTCHER STEVEN H
IPC: C23C16/34 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532 , H01L21/44 , H01L21/4763
Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.
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