公开(公告)号：CA2245633A1

公开(公告)日：1999-03-18

申请号：CA2245633

申请日：1998-08-14

Applicant: IBM

Inventor： KAHLE JAMES A ,  TRAN CANG N

IPC: G06F13/364 ,  G06F15/167

Abstract: A method and system for enhanced bus access in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wid e bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple pro cessors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a maximum-permitted number of sub-buses. If the number of sub-buses granted to a particular processor equals the number of pendi ng transactions at that processor, all pending transactions are performed in parall el on separate sub-buses. If the number of sub-buses granted is less than the number o f pending transactions, pending transactions are performed in a priority order. Fi nally, if the number of granted sub-buses is greater than the number of pending transactions, selected transactions are performed over multiple sub-buses in parallel, greatly enhancin g the speed of those transactions.

公开(公告)号：CA2107045A1

公开(公告)日：1994-07-09

申请号：CA2107045

申请日：1993-09-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG

IPC: G06F9/38 ,  G06F9/30

Abstract: A method and system for increased instruction synchronization efficiency in a superscalar processor system which includes instructions having multiple source and destination operands. Simultaneous dispatching of multiple instructions creates a source-to-destination data dependency problem in that the results of one instruction may be necessary to accomplish execution of a second instruction. Data dependency hazards may be eliminated by prohibiting each instruction from dispatching until all possible data dependencies have been eliminated by the completion of preceding instructions; however, instruction dispatch efficiency is substantially decrease d utilizing this technique. Data dependency interlock circuitry may be utilized to clear possible data dependency hazards; however, the complexity of such circuitry increases dramatically as the number of interlocked sources and destinations increases. The method and system of the present invention utilizes data dependency interlock circuitry capable of interlocking two source operands by two destination operands for each instruction. Instructions having three or more source operands are interlocked at the dispatch stage for the first two source operands utilizing existing data dependency interlock circuitry. Thereafter, the instruction is dispatched only after data dependency hazards are cleared for the first two source operands, utilizing the data dependency interlock circuitry, and all instructions preceding the instruction have been completed, eliminating possible data dependency hazards for the third source operand. In this manner, instructions which include three source operands may be synchronized without requiring a substantial increase in data dependency interlock circuitry and with only a slight degradation in system efficiency.

公开(公告)号：DE69322064T2

公开(公告)日：1999-07-01

申请号：DE69322064

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：CA2245037A1

公开(公告)日：1999-03-18

申请号：CA2245037

申请日：1998-08-14

Applicant: IBM

Inventor： KAHLE JAMES A ,  TRAN CANG N

IPC: G06F13/364 ,  G06F13/40 ,  G06F15/17

Abstract: A method and system for enhanced bus arbitration in a multiprocessor system havi ng multiprocessors coupled to a system memory via a common wide bus. The common wid e bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple pro cessors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a arbitration logic for a number of sub-b uses. A maximum number of sub-buses is specified for each processor and the processors a re prioritized. Each time a bus request is received from a processor, the number of requested sub-buses is granted, if that number is equal to or less than the specified maxi mum number of sub-buses for that processor. If the requested number of sub-buses is greater than the specified maximum number of sub-buses for that processor the requested number is granted if no other processor has issued a bus request.

公开(公告)号：AT173345T

公开(公告)日：1998-11-15

申请号：AT93120943

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：CA2107305A1

公开(公告)日：1994-07-09

申请号：CA2107305

申请日：1993-09-29

Applicant: IBM

Inventor： KAHLE JAMES A ,  WALDECKER DONALD E

IPC: G06F9/38 ,  G06F15/16

Abstract: A method and system for permitting nonsequential instruction dispatch in a superscalar processor system which dispatches sequentially ordered multiple instructions simultaneously to a group of execution units on an opportunistic basis for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the results of the execution of each instruction to be stored within an intermediate storage buffer. An indication of the status of each instruction is maintained within a completion buffer and thereafter utilized to selectively transfer results within the intermediate storage buffers to selected general purpose registers in an ordered consistent with an application specified sequential order. The occurrence of an interrupt which prohibits completion of a selected instruction can therefore be accurately identified within the completion buffer.

公开(公告)号：CA2107304A1

公开(公告)日：1994-07-09

申请号：CA2107304

申请日：1993-09-29

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  TU PAUL K ,  WALDECKER DONALD E

IPC: G06F9/38 ,  G06F15/16

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：CA2107046A1

公开(公告)日：1994-07-09

申请号：CA2107046

申请日：1993-09-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D

IPC: G06F9/38 ,  G06F9/30

Abstract: A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.

公开(公告)号：CA1321655C

公开(公告)日：1993-08-24

申请号：CA608713

申请日：1989-08-18

Applicant: IBM

Inventor： GROHOSKI GREGORY F ,  KAHLE JAMES A ,  NGUYENPHU MYHONG ,  RAY DAVID S

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48

Abstract: AT9-88-080 TIGHTLY COUPLED MULTIPROCESSOR INSTRUCTION SYNCHRONIZATION A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：DE69636861T2

公开(公告)日：2007-07-05

申请号：DE69636861

申请日：1996-08-29

Applicant: IBM

Inventor： KAHLE JAMES A ,  LOPER ALBERT J ,  MALLICK SOUMMYA ,  OGDEN AUBREY D

IPC: G06F9/312 ,  G06F9/38 ,  G06F12/00

Abstract: A load multiple instruction may be executed in a superscaler microprocessor by dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. A table is maintained that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. An instruction is executed that is dependent upon source operand data loaded by the load multiple instruction, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, a store multiple instruction may be executed by dispatching a store multiple instruction to the load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load/store instruction stores data from a plurality of registers to memory. A fixed point instruction is executed that is dependent upon data being stored by the store multiple instruction prior to the store multiple instruction completing its execution, but the executing fixed point instruction is prohibited from writing to a register of the plurality of registers prior to the store multiple instruction completing.