公开(公告)号：JP2005123597A

公开(公告)日：2005-05-12

申请号：JP2004271982

申请日：2004-09-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AJMERA ATUL C ,  BRYANT ANDRES ,  GILBERT PERCY V ,  GRIBELYUK MICHAEL A ,  MACIEJEWSKI EDWARD P ,  MO RENEE T ,  NARASIMHA SHREESH

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/02063 ,  H01L21/31116 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a gate electrode that avoids dielectric layer undercut during a silicide precleaning step. SOLUTION: A patterned gate stack includes a gate dielectric below a conductor having vertical sidewalls, and a dielectric layer is formed over the patterned gate stack and substrate surfaces. Nitride spacers are formed overlying the dielectric layer at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample and subsequently removed by an etch process such that only a portion of the nitride film ("plug") remains. The plug seals and encapsulates the dielectric layer underlying the each spacer, thus preventing the dielectric material from being undercut during the subsequent silicide precleaning process. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在硅化物预清洗步骤期间形成避免电介质层底切的栅电极的方法。 解决方案：图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，并且在图案化的栅极堆叠和衬底表面上形成介电层。 在每个垂直侧壁处形成覆盖电介质层的氮化物间隔物。 使用蚀刻工艺去除衬底表面上的电介质层，使得每个间隔物下面的电介质层的一部分保留。 然后，在整个样品上沉积氮化物层，然后通过蚀刻工艺去除，使得只有一部分氮化膜（“插塞”）保留。 塞子密封并封装每个间隔物下面的电介质层，从而防止在随后的硅化物预清洗过程中电介质材料被切下。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2010258471A

公开(公告)日：2010-11-11

申请号：JP2010155374

申请日：2010-07-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHANG LELAND ,  CHOU ANTHONY I ,  NARASIMHA SHREESH ,  SLEIGHT JEFFREY W

IPC: H01L29/786 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To mount a body contact on a semiconductor-on-insulator device, thereby reducing parasitic capacitance in the device. SOLUTION: A substrate includes a semiconductor layer arranged so as to be covered on an insulating layer. The semiconductor layer includes the substrate including a semiconductor body and an separation region existing around the outer periphery of the semiconductor body, and a gate structure covered on the semiconductor layer of the substrate. A method for manufacturing a semiconductor device is provided. The semiconductor device includes the gate structure existing on a first part of an upper face of the semiconductor body and a silicide body contact directly physically brought into contact with a second part of the semiconductor body separated from the first part of the semiconductor body by a non-silicide semiconductor region. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：将绝缘体上的半导体器件接触，从而减少器件中的寄生电容。 解决方案：衬底包括布置成被覆盖在绝缘层上的半导体层。 半导体层包括包括半导体本体的基板和存在于半导体主体的外周周围的分离区域，以及覆盖在基板的半导体层上的栅极结构。 提供一种制造半导体器件的方法。 该半导体器件包括存在于半导体本体的上表面的第一部分上的栅极结构和直接物理地与半导体本体的第一部分分离的半导体主体的第二部分接触的硅化物体接触， 硅化物半导体区域。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008182243A

公开(公告)日：2008-08-07

申请号：JP2008014311

申请日：2008-01-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHOU ANTHONY I-CHIH ,  MO RENEE T ,  NARASIMHA SHREESH

IPC: H01L21/316 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a high-quality, high-K dielectric material for an integrated circuit. SOLUTION: A method includes steps of: forming a material on a substrate; and patterning the material and removing a portion of the material to expose the portion of the substrate underlying the portion of the material. The method further includes a step of performing an oxidation process to form oxide layers over the exposed portion of the substrate and an interface between the material and the substrate. A circuit includes a non-critical device and an oxide formed as a portion of this non-critical device. A high-K dielectric material is formed over a substrate as a portion of the critical device within the circuit. An oxide-based interface is provided between the high-K dielectric material and the underlying substrate. A second method forms a nitride or oxynitride as a starting material. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为集成电路提供高品质，高K电介质材料。 解决方案：一种方法包括以下步骤：在衬底上形成材料; 以及图案化所述材料并去除所述材料的一部分以暴露所述材料部分下方的所述基底的所述部分。 该方法还包括进行氧化处理以在衬底的暴露部分和材料与衬底之间的界面上形成氧化物层的步骤。 电路包括非关键器件和形成为该非关键器件的一部分的氧化物。 作为电路内的关键器件的一部分，在衬底上形成高K电介质材料。 在高K电介质材料和下面的衬底之间提供氧化物基界面。 第二种方法形成氮化物或氧氮化物作为原料。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：WO2012064912A2

公开(公告)日：2012-05-18

申请号：PCT/US2011060084

申请日：2011-11-10

Applicant: IBM ,  JOHNSON JEFFREY B ,  NARASIMHA SHREESH ,  NAYFEH HASAN M ,  ONTALUS VIOREL C ,  ROBINSON ROBERT R

Inventor： JOHNSON JEFFREY B ,  NARASIMHA SHREESH ,  NAYFEH HASAN M ,  ONTALUS VIOREL C ,  ROBINSON ROBERT R

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7824 ,  H01L21/76237 ,  H01L21/84 ,  H01L27/1203

Abstract: A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer (105; Fig. 5) on a buried oxide (BOX) layer (115) of a silicon-on-insulator substrate (100); a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer (160, 165, and 170), a doped region (155) in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer (160), doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer (165), doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

Abstract translation: 一种结构，一种FET，一种制造该结构和制造该FET的方法。 所述结构包括：在绝缘体上硅衬底（100）上的掩埋氧化物（BOX）层（115）上的硅层（105;图5）; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层（160,165和170），所述硅层中的掺杂区域（155）和邻接 BOX层和沟槽的底部，掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层（160）; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层（165）; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

公开(公告)号：WO2006063060A3

公开(公告)日：2006-11-16

申请号：PCT/US2005044281

申请日：2005-12-08

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/31 ,  H01L23/58

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

Abstract translation: 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET（300）提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫（360）施加到器件上，并施加与快速氮化硅衬垫相邻的第二氮化硅衬垫（370） ，其中所述第一和第二氮化硅衬垫中的至少一个在所述第一和第二氮化硅衬垫中的至少一个下方的硅沟道（330）中引起横向应力。

公开(公告)号：DE112012004134B4

公开(公告)日：2017-09-07

申请号：DE112012004134

申请日：2012-10-26

Applicant: IBM

Inventor： BRODSKY MARY JANE ,  CAI MING ,  GUO DECHAO ,  HENSON WILLIAM K ,  NARASIMHA SHREESH ,  LIANG YUE ,  SONG LIYANG ,  WANG YANFENG ,  YEH CHUN-CHEN

IPC: H01L21/336

Abstract: Verfahren zum Fertigen von Transistoreinheiten, das aufweist: Bereitstellen einer Siliciumschicht, die eine Schicht eines Abschirmoxids aufweist, die auf einer oberen Fläche ausgebildet Ist; Aufbringen einer ersten Maskierungsschicht in einer Weise, dass ein erster Abschnitt der Abschirmoxidschicht unbedeckt bleibt; Implantieren von Kohlenstoff in die Siliciumschicht durch den unbedeckten ersten Abschnitt der Abschirmoxidschicht, um ein erstes mit Kohlenstoff implantiertes Volumen der Siliciumschicht mit einer ersten Kohlenstoffkonzentration auszubilden; Entfernen der ersten Maskierungsschicht; Aufbringen einer zweiten Maskierungsschicht in einer Weise, dass ein zweiter Abschnitt der Abschirmoxidschicht unbedeckt bleibt; Implantieren von Kohlenstoff in die Siliciumschicht durch den unbedeckten zweiten Abschnitt der Abschirmoxidschicht, um ein zweites mit Kohlenstoff implantiertes Volumen der Siliciumschicht auszubilden, das eine zweite Kohlenstoffkonzentration aufweist, die sich von der ersten Kohlenstoffkonzentration unterscheidet; Entfernen der zweiten Maskierungsschicht; und ...

公开(公告)号：GB2486601B

公开(公告)日：2013-10-30

申请号：GB201203113

申请日：2010-08-25

Applicant: IBM

Inventor： LI YING ,  NARASIMHA SHREESH ,  RAUSCH WERNER A

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

Abstract: Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.

公开(公告)号：GB2486601C

公开(公告)日：2013-11-27

申请号：GB201203113

申请日：2010-08-25

Applicant: IBM

Inventor： LI YING ,  NARASIMHA SHREESH ,  WERNER RAUSCH A

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

Abstract: Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI.

公开(公告)号：DE112011103730T5

公开(公告)日：2013-09-26

申请号：DE112011103730

申请日：2011-11-10

Applicant: IBM

Inventor： NARASIMHA SHREESH ,  ONTALUS VIOREL C ,  JOHNSON JEFFREY B ,  NAYFEH HASAN M

IPC: H01L29/78 ,  H01L21/336

Abstract: Eine Struktur, ein FET, ein Verfahren zum Herstellen der Struktur und zum Herstellen des FET. Die Struktur beinhaltet: eine Siliciumschicht (105; 5) auf einer vergrabenen Oxid(BOX)-Schicht (115) eines Silicium-auf-Isolator-Substrats (100); einen Graben in der Siliciumschicht, der sich von einer Oberseite der Siliciumschicht in die Siliciumschicht hinein erstreckt, wobei sich der Graben nicht bis zu der BOX-Schicht (160, 165, und 170) erstreckt, einen dotierten Bereich (155) in der Siliciumschicht zwischen der BOX-Schicht und einem Boden des Grabens und an diese angrenzend, wobei der erste dotierte Bereich bis zu einer ersten Dotierstoffkonzentration dotiert ist; eine erste epitaxiale Schicht (160) in einem Boden des Grabens, die bis zu einer zweiten Dotierstoffkonzentration dotiert ist; eine zweite epitaxiale Schicht (165) auf der ersten epitaxialen Schicht in dem Graben, die bis zu einer dritten Dotierstoffkonzentration dotiert ist; und wobei die dritte Dotierstoffkonzentration höher als die erste und zweite Dotierstoffkonzentration ist und die erste Dotierstoffkonzentration höher als die zweite Dotierstoffkonzentration ist.

公开(公告)号：GB2514709A

公开(公告)日：2014-12-03

申请号：GB201415474

申请日：2013-02-19

Applicant: IBM

Inventor： SLEIGHT JEFFERY W ,  CHANG JOSEPHINE B ,  LAUER ISSAC ,  NARASIMHA SHREESH

IPC: H01L29/423 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Non-planar semiconductor devices are provided that include at least one semiconductor nanowire 18" suspended above a semiconductor oxide layer (26) that is present on a first portion (100) of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region (20A) and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region (20B). The first and second pad regions are located above and are in direct contact with a second portion (102) of the bulk semiconductor substrate which is vertically offsets from the first portion (100). The structure further includes a gate (27) surrounding a central portion (18C) of the at least one semiconductor nanowire, a source region (40, 50A) located on a first side of the gate, and a drain region (40', 50B) located on a second side of the gate which is opposite the first side of the gate.