公开(公告)号：CA2131668A1

公开(公告)日：1995-06-24

申请号：CA2131668

申请日：1994-09-08

Applicant: IBM

Inventor： GALLI CAROL ,  HSU LOUIS L ,  OGURA SEIKI ,  SHEPARD JOSEPH F

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L27/08 ,  H01L21/31

Abstract: A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. First, a trench (18) is formed in a silicon substrate (12) having a thin blanket layer (14) of a hard polish-stop material and a photo resist layer (16) (used to pattern the structure) formed thereon. A channel stop region (20) is formed as standard in the trench. Next, the trench is filled with SiO2 using liquid phase oxide deposition above the level of said thin layer. Then the photo resist layer is removed and the SiO2 fill (22) is planarized. Finally, the SiO2 fill is densified and during the thermal cycle, a thin layer (30) of thermal oxide is formed at the fill-substrate interface. The structure can be readily and easily planarized, and voids contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on the resist used to form the trench.

公开(公告)号：CA1290079C

公开(公告)日：1991-10-01

申请号：CA601597

申请日：1989-06-02

Applicant: IBM

Inventor： AKBAR SHAH ,  KROESEN PATRICIA L ,  OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L29/73 ,  G03C3/00 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L29/72 ,  H01L29/52 ,  H01L29/60

Abstract: VERTICAL BIPOLAR TRANSISTOR A Compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer;a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer. The structure further includes a base contact interconnect disposed on a surface of the base contact extension layer and; a collector contact extension layer formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers. FI9-87-027

公开(公告)号：CA2011233A1

公开(公告)日：1990-12-09

申请号：CA2011233

申请日：1990-03-01

Applicant: IBM

Inventor： CODELLA CHRISTOPHER F ,  ROVEDO NIVO ,  OGURA SEIKI

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76

Abstract: FIELD-EFFECT-TRANSISTOR WITH ASYMMETRICAL STRUCTURE A field effect transistor of asymmetrical structure comprises: a semiconductor substrate of first conductivity type; source and drain regions of second conductivity type disposed in a surface of the substrate and spaced apart by a channel region; and a single, lightly doped extension of the drain region into the channel, the extension being of the second conductivity type and of a lower dopant concentration than the drain region. The transistor can further beneficially comprise a halo region of the first conductivity type in the substrate generally surrounding only the source region.

公开(公告)号：BR8903812A

公开(公告)日：1990-03-20

申请号：BR8903812

申请日：1989-07-31

Applicant: IBM

Inventor： AKBAR SHAH ,  KROESEN PATRICIA LAVELLE ,  OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L29/73 ,  G03C3/00 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L29/70

Abstract: A Compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer (12); a base layer (14) disposed over the collector layer; an emitter layer (16) disposed over the base layer; a first sidewall insulating layer (18) disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer (20) disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer (22) formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer. The structure further includes a base contact interconnect (24) disposed on a surface of the base contact extension layer and; a collector contact extension layer (26) formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect (29) disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers.

公开(公告)号：AU579764B2

公开(公告)日：1988-12-08

申请号：AU6995987

申请日：1987-03-12

Applicant: IBM

Inventor： DALLY ANTHONY JOHN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/762

Abstract: A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

公开(公告)号：DE69302960D1

公开(公告)日：1996-07-11

申请号：DE69302960

申请日：1993-03-23

Applicant: IBM

Inventor： DOERRE GEORGE WILLIAM ,  OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84 ,  H01L21/302

Abstract: An SOI wafer (10/20) has an epitaxial device layer (30) of initial thickness that is formed into a set of mesas (40) in the interval between which a temporary layer (42) of polysilicon is blanket deposited to a precisely controlled thickness. This polysilicon is entirely converted in a self-limiting process to an oxide etch stop pads (45) (having a thickness greater than the initial thickness) except on the mesa side walls. The mesas are thinned by a chemical mechanical polishing technique until the mesa is the same level as the top surface of the new oxide. The etch stop layer of oxide forming pads (45) is not removed but serves both as an isolating layer to provide dielectric isolation between final mesas (40') in the final circuit and also as a visual gauge to determine the time when the polishing process should stop.

公开(公告)号：DE3688042T2

公开(公告)日：1993-09-16

申请号：DE3688042

申请日：1986-10-10

Applicant: IBM

Inventor： OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO ,  SCHULZ RONALD N

IPC: G03F1/00 ,  G03F1/08 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/00 ,  H01L21/76

公开(公告)号：DE3681696D1

公开(公告)日：1991-10-31

申请号：DE3681696

申请日：1986-07-29

Applicant: IBM

Inventor： BEYER KLAUS DIETRICH ,  MAKRIS JAMES STEVE ,  MENDEL ERIC ,  NUMMY KAREN ANN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763

Abstract: A chemical-mechanical (chem-mech) method for removing SiO₂ protuberances at the surface of a silicon chip, such protuberances including "bird heads". A thin etch stop layer of Si₃N₄ (29) is deposited onto the wafer surface, which is then chem-mech polished with a SiO₂ water based slurry. The Si₃N₄ acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si₃N₄ layer located on the top and at the sidewalls of the "bird' heads" and the underlying SiO₂ protuberances are removed to provide a substantially planar integrated structure.

公开(公告)号：DE3766737D1

公开(公告)日：1991-01-31

申请号：DE3766737

申请日：1987-02-11

Applicant: IBM

Inventor： BALASUBRAMANYAM KARANAM ,  RISEMAN JACOB ,  DALLY ANTHONY JOHN ,  OGURA SEIKI

IPC: H01L21/3205 ,  G03F7/09 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/90 ,  G03F7/26

Abstract: Disclosed is a process of forming high density, planar, single- or multi-level wiring for an semiconductor integrated circuit chip. On the chip surface (10) is provided a dual layer of an insulator (14) and hardened photoresist (16) having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer (22) of a thickness equal to that of the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist (28, 30) is formed filling the metal valleys and obtaining a substantially planar surface (32). The lower component layer (28) is thin and conformal and has a higher etch rate than the upper component layer (30) which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photo-resist layer and the plugs leaving a metal pattern coplanar with the insulator layer. This sequence of steps is repeated for multilevel wiring. When only narrow wiring is desired, a single photoresist layer is substituted for the dual photo-resist sacrificial layer.

公开(公告)号：CA1273274A

公开(公告)日：1990-08-28

申请号：CA508583

申请日：1986-05-07

Applicant: IBM

Inventor： BEYER KLAUS D ,  MAKRIS JAMES S ,  MENDEL ERIC ,  NUMMY KAREN A ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/205

Abstract: A chemical-mechanical (chem-mech) method for removing SiO2 protuberances at the surface of a silicon chip, such protuberances including "bird heads". A thin etch stop layer of Si3N4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO2 water based slurry. The Si3N4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si3N4 layer located on the top and at the sidewalls of the "bird' heads" and the underlying SiO2 protuberances are removed to provide a substantially planar integrated structure.