公开(公告)号：JPH11260935A

公开(公告)日：1999-09-24

申请号：JP4799

申请日：1999-01-04

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a cap self-aligned on a gate conductor, and realize a two actional function for selectively applying P doping and N doping to the gate conductor. SOLUTION: A selected number of gate structures having self-aligned insulating layers 2 and 4 are doped by a first conductive type dopant through at least one sidewall of the gate structure. Thus, one gate structure is doped with the first conductive dopant, and another gate structure is doped with a second and different conductive dopant in this gate structural array. Therefore, a two actional function can be given.

公开(公告)号：JP2007227920A

公开(公告)日：2007-09-06

申请号：JP2007037510

申请日：2007-02-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  TONTI WILLIAM R ,  HORAK DAVID VACLAV ,  ETHAN HARRISON CANNON ,  FURUKAWA TOSHIHARU ,  CHARLES WILLIAM KOBURGER III ,  JIMMY KONSTANTINOS KONTOS ,  HAKEY MARK C

IPC: H01L27/08 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor and a device structure which suppress the latch-up in a bulk CMOS device.
SOLUTION: The method includes a step of forming a trench in a semiconductor material of a substrate, while the trench has a first side wall disposed between a pair of doped wells demarcated in the semiconductor material of the substrate. The method further includes a step of forming an etching mask in the trench to mask partially the basal surface of the trench, and successively a step of removing the semiconductor material of the substrate exposing in the basal surface which has been partially masked and demarcating a second side wall which deepens the trench and has been narrowed. A dielectric material is filled in the deepened trench to demarcate trench separation regions of devices constructed in the doped wells. The dielectric material filled in the extended part of the deepened trench improves the suppression of the latch-up.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造半导体的方法和抑制体CMOS器件中的闩锁的器件结构。 解决方案：该方法包括在衬底的半导体材料中形成沟槽的步骤，而沟槽具有设置在衬底的半导体材料中划分的一对掺杂阱之间的第一侧壁。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩模沟槽的基面的步骤，并且连续地去除已经被部分掩蔽并且划分第二个的基底表面中露出的衬底的半导体材料的步骤 侧壁加深了沟槽并缩小了。 将介电材料填充在加深的沟槽中以划定在掺杂阱中构造的器件的沟槽分离区域。 填充在加深沟槽的延伸部分中的电介质材料改善了闩锁的抑制。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004056119A

公开(公告)日：2004-02-19

申请号：JP2003160554

申请日：2003-06-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  MANDELMAN JACK ALLAN ,  TONTI WILLIAM R

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L21/76237

Abstract: PROBLEM TO BE SOLVED: To improve a leakage current characteristic at or below the threshold of a trench discrete type FET element.
SOLUTION: A slot in a vertical direction is formed in an stacked structure 14 adhered to a silicon substrate 10 covered with an oxide 12, and thereafter a spacer is formed on the sidewall of the slot. Then, a trench is formed in the substrate 10 by etching. A horizontal ledge appears adjacent to the trench, on the exposed surface of the substrate covered with the oxide by removal of the spacer. The conduction of an end in the element is suppressed by injecting a proper impurity into this ledge.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提高等于或低于沟槽离散型FET元件的阈值的漏电流特性。 解决方案：垂直方向的槽形成在粘附到被氧化物12覆盖的硅衬底10上的堆叠结构14中，然后在槽的侧壁上形成间隔件。 然后，通过蚀刻在衬底10中形成沟槽。 水平凸缘出现在沟槽附近，通过移除间隔件，在被氧化物覆盖的基板的暴露表面上。 通过在该凸缘中注入适当的杂质来抑制元件中端部的导通。 版权所有（C）2004，JPO

公开(公告)号：JP2003303898A

公开(公告)日：2003-10-24

申请号：JP2003078141

申请日：2003-03-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： BERTIN CLAUDE L ,  JOHN JOSEF ELLIS-MONAHAN ,  ERIK RAY HEDBERG ,  HOOK TERENCE B ,  MANDELMAN JACK ALLAN ,  EDWARD JOSEF NOWACK ,  PRICER WILBUR DAVID ,  MIN HO TON ,  TONTI WILLIAM R

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H03K17/06 ,  H03K19/00 ,  H03K19/094 ,  H03K19/0944

CPC classification number: H03K19/0027 ,  H01L29/78606 ,  H03K2217/0018

Abstract: PROBLEM TO BE SOLVED: To provide a switched body SOI CMOS circuit which is provided with an FET element for increasing a FET element threshold voltage.
SOLUTION: A circuit having an SOI element is connected with a body bias voltage, via a switch for selectively connecting a body bias voltage signal with an SOI element body. An NMOS or PMOS SOI element is used as the switched body SOI element. An FET is used as a switch. A gate terminal of the SOI element is connected with an FET element. A gate of the SOI element controls the FET switch connection of the body bias voltage signal to the SOI element, and adjusts a threshold value voltage of the SOI element. A logic circuit including the SOI element and a fabrication process for the SOI element are similarly disclosed.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种开关体SOI CMOS电路，其提供有用于增加FET元件阈值电压的FET元件。 解决方案：具有SOI元件的电路通过用于选择性地将体偏置电压信号与SOI元件体连接的开关与体偏置电压连接。 NMOS或PMOS SOI元件用作开关体SOI元件。 使用FET作为开关。 SOI元件的栅极端子与FET元件连接。 SOI元件的栅极控制体偏置电压信号与SOI元件的FET开关连接，并调整SOI元件的阈值电压。 类似地公开了包括SOI元件的逻辑电路和用于SOI元件的制造工艺。 版权所有（C）2004，JPO

公开(公告)号：JPH11168190A

公开(公告)日：1999-06-22

申请号：JP27728998

申请日：1998-09-30

Applicant: SIEMENS AG ,  IBM

Inventor： MANDELMAN JACK A ,  HSU LOUIS L C ,  ALSMEIER JOHANN ,  TONTI WILLIAM R

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a small trench capacitor having sufficiently low parasitic leakage. SOLUTION: A transistor, which includes a gate and first and second diffused regions are provided. A trench capacitor in a substrate electrically connects a dielectric color part 168 at the upper-side part of a trench, a diffused region embedded in a substrate surrounding the lower part of the trench capacitor, a transitor and the capacitor. A node diffused region is included on a collar part. A third diffused region 269 is provided in a substrate neighboring the color part. In order to decrease the leakage, an adequate concentration of doping agent for enhancing the threshold voltage of the gate of a parasitic transistor, which is formed of the color part, the embedded diffused region and node diffusion, is provided.

公开(公告)号：JP2004088101A

公开(公告)日：2004-03-18

申请号：JP2003287197

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  BROWN JEFFREY S ,  FRIED DAVID M ,  GAUTHIER JR ROBERT J ,  EDWARD J NOWAKU ,  RANKIN JED H ,  TONTI WILLIAM R

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

Abstract: PROBLEM TO BE SOLVED: To provide an improved manufacturing method of an integrated circuit which is made by incorporating both a FinFET and a thick-body device into a single chip. SOLUTION: This manufacturing method of a microelectronic circuit which is made by incorporating both a fin-type field-effect transistor (FinFET) 1801 and a thick-body device 1802 into a single chip can attain an efficiency higher than that of the conventional methods by utilizing common masks and processes. Reduction in the numbers of masks and processes is achieved by utilizing common masks and processes together with several reduction strategies. For example, a structure which usually accompanies a FinFET is formed on a side surface of a thick silicon mesa. A bulk of the silicon mesa is doped to connect to a body contact formed on the opposite side surface of the mesa. This invention also includes the FinFET, thick-body device, and a chip manufactured by the methods associated with the invention. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002319674A

公开(公告)日：2002-10-31

申请号：JP2002035743

申请日：2002-02-13

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  DALLY ANTHONY J ,  FIFIELD JOHN ATKINSON ,  HIGGINS JOHN JESSE ,  MANDELMAN JACK ALLAN ,  TONTI WILLIAM R ,  HEEL NICHOLAS MARTIN VAN

IPC: H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor equipped having a dielectric layer of two-dimensional thickness, and to provide a method of manufacturing the same. SOLUTION: This manufacturing method comprises a first process of forming a mask with a through-hole 20 equipped with a side wall 21 on a structure (a), a second process of implanting suppression chemical seeds 24 into the structure through the through-hole 20 so as to form a suppression region 26 in the structure (b), and a third process of enabling a dielectric layer 28 to grow on the structure in the through-hole 20. Here, the suppression region 26 restrains the dielectric layer 28 partially from growing. By this setup, a self-aligned MOSFET or an anti-fuse device having a low overlap capacitance and a low gate induction drain leakage (i.e., low electric field) can be formed.

公开(公告)号：JP2002270697A

公开(公告)日：2002-09-20

申请号：JP2002021072

申请日：2002-01-30

Applicant: IBM

Inventor： BROWN JEFFREY S ,  GAUTHIER ROBERT J JR ,  RANKIN JED H ,  TONTI WILLIAM R

IPC: H01L27/04 ,  H01L21/763 ,  H01L21/768 ,  H01L21/822 ,  H01L27/00 ,  H01L27/02 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide efficient heat radiation which is related to an SOI structure, by forming a semiconductor device located beneath an embedded insulation layer, which is in turn electrically connected to an electrical structure body formed on the SOI structure. SOLUTION: The SOI structure is formed on a bulk semiconductor substrate. A trench, whose one end interfaces with the bulk semiconductor substrate is formed penetrating through the SOI layer. A semiconductor device, comprising a P diffusion region and N diffusion region, is formed on the bulk semiconductor substrate. A conductive plug, which self-matching with the P diffusion region and N diffusion region, while electrically contacting them, is formed in the trench. The semiconductor device formed in the bulk semiconductor substrate can contain an electrostatic discharge(ESD) device. The bulk semiconductor substrate functions as a medium for efficiently radiating heat generated by the (ESD) device, since its thermal conductivity is high.

公开(公告)号：JP2001345383A

公开(公告)日：2001-12-14

申请号：JP2001160548

申请日：2001-05-29

Applicant: IBM

Inventor： CLAUDEL L BARTIN ,  RAMACHANDORA DEIVAKARUNI ,  HOUGHTON RUSSELL J ,  MANDELMAN JACK A ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide an anti-fuse structure which can program at a low voltage and current, uses only in an extremely small chip base, and can be formed in a gap between parts which are disposed at intervals of a least lithographic feature size. SOLUTION: An anti-fuse structure is formed on an SOI substrate in combination with a capacitor-like structure which reaches support layer or in the support layer by etching a contact which penetrates an insulator and reaches the support semiconductor layer. This anti-fuse can be programmed by selecting a position forming a conductor or damaging a dielectric of the capacitor-like structure. It is possible to restrict the damages to a desirable position by use of an insulation collar enclosing the conductor or a part of the capacitor-like structure. Thermal influences due to a programming current are isolated into the interior of a bulk silicon layer, whereby a programming during a normal operation of a device is enabled.

公开(公告)号：JP2001007223A

公开(公告)日：2001-01-12

申请号：JP2000160941

申请日：2000-05-30

Applicant: IBM

Inventor： JEFFREY P GANBINO ,  LEWIS L SUU ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function gate conductor having a self-aligned insulating cap, and a method for forming the dual work function gate conductor. SOLUTION: Two diffusion regions 36 are formed on a substrate 20, and gate stacks 33 and 34 are formed on the substrate 20 between these regions 36. The stacks 33 and 34 have a gate insulating layer 24, and polysilicon layers 26 and 26a on the layer 24, respectively. The layers 26 and 26a are n-type doped and remain intrinsic. A barrier layer 28 is formed on each of the layers 26 and 26a. A dopant source 30 is formed on the layer 28 for both stacks 33 and 34. The layer 28 has a p-type dopant. The stacks 33 and 34 are covered with an insulating cap 32 so that diffusion contacts can be formed on the gates in a borderless manner. When to start activating the source 30 for doping the layers 26 and 26a can be postponed until the desired timing.