公开(公告)号：AU2003292985A8

公开(公告)日：2004-06-18

申请号：AU2003292985

申请日：2003-11-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS ,  WERNER WOLFGANG ,  KLOSE HELMUT

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/8246 ,  H01L27/112

Abstract: A semiconductor memory device with a phase transformation memory effect includes at least one memory element in a semiconductor substrate, and a cavity arrangement including at least one cavity in spatial proximity to the respective memory element. The cavity is in spatial arrangement with the respective memory element so as to reduce thermal coupling of the respective memory element to the areas surrounding the memory element, which also reduces the thermal conductivity between memory element and the areas surrounding the memory element.

公开(公告)号：DE10219396A1

公开(公告)日：2003-11-20

申请号：DE10219396

申请日：2002-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOERT MANFRED ,  MIKOLAJICK THOMAS

IPC: G11C11/22

Abstract: The memory cell contains a storage capacitor (C) formed by two electrodes (BE,TE) sandwiching ferroelectric dielectric storage region (F), containing several ferroelectric sections (F1...Fn). Pairs of sections have different characteristics, e.g. electric properties. Due to the different characteristics, can be formed in the sections a corresponding number of binary individual polarisation states (P1...Pn). Thus a number of binary bits can be stored in storage capacitor. Independent claims are included for semiconductor memory and method of operation of the memory cell.

公开(公告)号：DE10131491A1

公开(公告)日：2003-01-16

申请号：DE10131491

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL ,  WEINRICH VOLKER

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8239

Abstract: Production of a semiconductor storage device comprises: forming a semiconductor substrate (20), a passivating region (21) and/or a surface region (20a, 21a) with a complementary metal oxide semiconductor (CMOS) structure; forming capacitor arrangements (10-1,..., 10-4); and contacting the capacitor arrangements with the CMOS structure using contact regions or plug regions (P1, P2). At least one part of the contact regions or plug regions are formed with a region raised above the surface region of the passivating region. Preferred Features: The contact regions or plug regions are formed in a common process step, preferably after forming the passivating region.

公开(公告)号：DE10105673A1

公开(公告)日：2002-09-05

申请号：DE10105673

申请日：2001-02-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KASKO IGOR ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/8239

Abstract: Production of a stacked integrated ferroelectric semiconductor storage device or a DRAM cell comprises depositing an oxygen barrier (3) between a capacitor electrode (4) and an electrically conducting plug (1) which connects the electrode to a semiconductor electrode; and carrying out a rapid thermal processing step at 700-1000 deg C, preferably 800-900 deg C, after depositing the ferroelectric or high iota -material dielectric but before tempering. An Independent claim is also included for an integrated DRAM cell produced. Preferred Features: The temperature of the tempering step is below the temperature of the rapid thermal processing step. The oxygen barrier is made from Ir/IrOx.

公开(公告)号：DE10105997C1

公开(公告)日：2002-07-25

申请号：DE10105997

申请日：2001-02-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239

Abstract: Production of a ferroelectric capacitor in integrated semiconductor storage chips comprises forming an adhesion layer (3) unstructured in a region containing ferroelectric capacitors (10, 11) between a conducting plug (1a, 1b) and an oxygen barrier (4a, 4b); exposing the adhesion layer in sections by oxidizing using the oxygen barrier; and converting into an insulating layer. Preferably the adhesion layer contains tantalum. The conducting plug is made from polysilicon or tungsten. The oxidized sections extend below the edge regions of the oxygen barrier.

公开(公告)号：DE10065669A1

公开(公告)日：2002-07-11

申请号：DE10065669

申请日：2000-12-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS ,  KASTNER MARCUS J

IPC: H01L21/8242 ,  H01L21/8246 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

Abstract: The invention relates to a method for producing an integrated semiconductor memory arrangement. According to said method, two capacitor modules (10, 20) are formed for each selection transistor (8) from the front and rear side of the substrate wafer (1) respectively. Said inventive process achieves a higher packing density of memory cells by the utilisation of the rear side of the wafer. A twofold memory read signal can be used for the same cell surface area. Conditions in addition to "0" or "1" can also be saved for each selection transistor (8) in a ferroelectric memory arrangement, if the two capacitor modules have a different structure in terms of layer thickness, surface area or material.

公开(公告)号：DE102006008503A1

公开(公告)日：2007-06-28

申请号：DE102006008503

申请日：2006-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER TORSTEN ,  OLLIGS DOMINIK ,  KUESTERS KARL-HEINZ ,  MIKOLAJICK THOMAS ,  POLEI VERONIKA ,  WILLER JOSEF

IPC: H01L21/8247 ,  G11C16/00

Abstract: A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

公开(公告)号：DE10131490B4

公开(公告)日：2006-06-29

申请号：DE10131490

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/8239 ,  H01L21/02 ,  H01L21/8242

公开(公告)号：DE10131625B4

公开(公告)日：2006-06-14

申请号：DE10131625

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/8239 ,  H01L27/105 ,  H01L21/02 ,  H01L27/115 ,  H01L27/11502

Abstract: To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.

公开(公告)号：DE102004006505B4

公开(公告)日：2006-01-26

申请号：DE102004006505

申请日：2004-02-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS

IPC: H01L21/8238 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76

Abstract: A memory cell patterned as a trench transistor is provided with a first gate electrode ( 4 ) as auxiliary gate for source-side injection and a second gate electrode ( 5 ) electrically insulated therefrom, which are arranged in the trench, and has, at the trench walls, a storage layer sequence ( 10 ) provided for charge trapping and comprising a storage layer ( 12 ) between boundary layers ( 11, 13 ). The first gate electrode ( 4 ) and the second gate electrode ( 5 ) are electrically insulated from one another, which can be effected by means of a portion of the storage layer sequence ( 10 ). Source/drain regions ( 3 ) are arranged on the top side laterally with respect to the trenches. Word lines ( 6 ), source/drain lines and control gate lines are present for the electrical driving.