公开(公告)号：EP3198405A4

公开(公告)日：2018-06-06

申请号：EP15844610

申请日：2015-09-10

Applicant: INTEL CORP

Inventor： MAIYURAN SUBRAMANIAM ,  STARKEY DARIN M ,  PIAZZA THOMAS A

IPC: G06F9/38 ,  G06F15/80

CPC classification number: G06F9/3887 ,  G06F8/443 ,  G06F8/452 ,  G06F9/30058 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30076 ,  G06F9/30134 ,  G06F9/30163 ,  G06F9/325 ,  G06F9/3842 ,  G06F9/3851

Abstract: An apparatus and method for a SIMD structured branching. For example, one embodiment of a processor comprises: an execution unit having a plurality of channels to execute instructions; and a branch unit to process control flow instructions and to maintain a per channel count for each channel and a control instruction count for the control flow instructions, the branch unit to enable and disable the channels based at least on the per channel count.

公开(公告)号：EP3198553A4

公开(公告)日：2018-04-04

申请号：EP15844016

申请日：2015-08-25

Applicant: INTEL CORP

Inventor： SHARMA SAURABH ,  MAIYURAN SUBRAMANIAM M ,  PIAZZA THOMAS A ,  BHIRAVABHATLA KALYAN K ,  DOYLE PETER L ,  JOHNSON PAUL A ,  PODDAR BIMAL ,  HASSELGREN JON N ,  MUNKBERG CARL J ,  AKENINE MOELLER TOMAS G ,  SYRJA HARRI ,  ROGOVIN KEVIN ,  FARRELL ROBERT L

IPC: G06T1/20 ,  G06T15/40 ,  G06T15/50 ,  G09G5/393

CPC classification number: G06T1/20 ,  G06T15/40 ,  G06T15/405 ,  G06T15/503 ,  G09G5/393

Abstract: In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.

公开(公告)号：GB2487328B

公开(公告)日：2012-10-03

申请号：GB201207247

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ALTUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：GB2471786B

公开(公告)日：2012-09-05

申请号：GB201015007

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ALTUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：HK1088417A1

公开(公告)日：2006-11-03

申请号：HK06110502

申请日：2006-09-21

Applicant: INTEL CORP

Inventor： JIANG HONG ,  PIAZZA THOMAS A

IPC: G06F20100101 ,  G06F9/46

Abstract: Multiple parallel passive threads of instructions coordinate access to shared resources using "active" semaphores. The semaphores are referred to as active because the semaphores send messages to execution and/or control circuitry to cause the state of a thread to change. A thread can be placed in an inactive state by a thread scheduler in response to an unresolved dependency, which can be indicated by a semaphore. A thread state variable corresponding to the dependency is used to indicate that the thread is in inactive mode. When the dependency is resolved a message is passed to control circuitry causing the dependency variable to be cleared. In response to the cleared dependency variable the thread is placed in an active state. Execution can proceed on the threads in the active state.

公开(公告)号：GB2336086B

公开(公告)日：2002-12-11

申请号：GB9907701

申请日：1999-04-01

Applicant: REAL 3 D INC ,  INTEL CORP

Inventor： HARTOG SCOTT ,  MANTOR MICHAEL ,  CAREY JOHN AUSTIN ,  PIAZZA THOMAS A ,  TAYLOR RALPH CLAYTON ,  RADECKI MATTHEW

IPC: G06F12/00 ,  G06F12/02 ,  G06T1/60 ,  G06T11/20 ,  G06T11/40 ,  G11C7/10 ,  G06T15/00

公开(公告)号：AU2715500A

公开(公告)日：2000-07-24

申请号：AU2715500

申请日：1999-12-21

Applicant: INTEL CORP

Inventor： PIAZZA THOMAS A ,  COOK VAL G

IPC: H04N7/32 ,  H03M7/30 ,  H03M7/36 ,  H03M7/40 ,  H04N7/36 ,  H04N7/26

Abstract: A method and apparatus for motion compensation of digital video data with a texture mapping engine is described. In general, the invention provides motion compensation by reconstructing a picture by predicting pixel colors from one or more reference pictures. The prediction can be forward, backward or bidirectional. The architecture described herein provides for reuse of texture mapping hardware components to accomplish motion compensation of digital video data. Bounding boxes and edge tests are modified such that complete macroblocks are processed for motion compensation. In addition, pixel data is written into a texture palette according to a first order based on Inverse Discrete Cosine Transform (IDCT) results and read out according to a second order optimized for locality of reference. A texture palette memory management scheme is provided to maintain current data and avoid overwriting of valid data when motion compensation commands are pipelined.

公开(公告)号：DE112009000373T5

公开(公告)日：2011-01-27

申请号：DE112009000373

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ALTUG ,  KAHN OPER

IPC: G06F12/00 ,  G06F9/00 ,  G06T1/00 ,  H04L12/00

公开(公告)号：BRPI0902504A2

公开(公告)日：2010-06-15

申请号：BRPI0902504

申请日：2009-07-30

Applicant: INTEL CORP

Inventor： DWYER MICHAEL K ,  FARRELL ROBERT L ,  HONG JIANG ,  PIAZZA THOMAS A

IPC: G06F9/48 ,  H04L12/56

公开(公告)号：HK1044838A1

公开(公告)日：2002-11-01

申请号：HK02106466

申请日：2002-09-02

Applicant: INTEL CORP

Inventor： CLOHSET STEVE J ,  DIEP TRUNG A ,  GANDHI WISHWESH ,  PIAZZA THOMAS A ,  SREENIVAS ADITYA ,  TRIEU TUONG P

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/18 ,  G06F13/362 ,  G06F

Abstract: According to one embodiment, a computer system is disclosed that includes a memory and a memory controller coupled to the memory. The memory controller includes an arbitration unit that may be programmed to operate according to a first arbitration mode or a second arbitration mode. The computer system also includes a first device and a second device coupled to the arbitration unit. According to a further embodiment, the first device is assigned a higher priority classification than the second device for accessing the memory while the arbitration unit is operating according to the first arbitration mode. In addition, the first device and the second device are assigned equal priority classifications for accessing the memory while the arbitration unit is operating according to the second arbitration mode.