公开(公告)号：WO2018182653A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025200

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N. ,  DARMAWIKARTA, Kristof Kuwawi ,  MAY, Robert Alan ,  ALEKSOV, Aleksandar ,  KAMGAING, Telesphor

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/485 ,  H01L23/00

Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.

公开(公告)号：WO2018125094A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/068942

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： UNRUH, David ,  PIETAMBARAM, Srinivas V.

IPC: H01L23/00 ,  H01L23/12 ,  H01L23/498

Abstract: Methods/structures of forming package structures are described. Those methods/structures may include forming a first conductive trace adjacent a second conductive trace on a dielectric material of a high density package substrate. A barrier layer is formed on at least one of the first conductive trace or the second conductive trace, wherein the barrier layer comprises a corrosion resistant material, and forming a conductive via on a portion of the barrier layer.

公开(公告)号：WO2018063263A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054559

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  BOYAPATI, Sri Ranga Sai ,  MAY, Robert A. ,  DARMAWIKARTA, Kristof ,  SOTO GONZALEZ, Javier ,  LIM, Kwangmo

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/525

CPC classification number: H01L23/5389 ,  H01L23/00 ,  H01L24/06 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2924/18162

Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

Abstract translation: 描述了基础层和形成导电通路的方法。 管芯焊盘形成在管芯上。 籽晶层沉积在管芯焊盘和基础层上。 在籽晶层上沉积第一光致抗蚀剂层，并且图案化第一层以形成在裸片焊盘上开口的导电线。 将导电材料沉积到导线开口中以形成导线。 在第一层上沉积第二光致抗蚀剂层，并且图案化第二层以在导电线上形成通孔开口。 将导电材料沉积到通孔开口中以形成导电通路，其中导电材料仅沉积在暴露的导电线路的部分上。 第二层和第一层被删除。 部分暴露的种子层凹陷，然后暴露导电通孔的顶部表面。

公开(公告)号：WO2017112223A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/063161

申请日：2016-11-21

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N.

IPC: H01L23/29 ,  H01L21/56

CPC classification number: B32B27/20 ,  B32B27/06 ,  B32B27/38 ,  B32B2457/00 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/145 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18

Abstract: This document discusses, among other things, a microelectronic system including a mold compound having a base layer and a surface layer on the base layer, and a seed layer deposited on the surface layer of the mold compound. The mold compound includes a monomer epoxy resin, a hardener, a filler material, and a polymer interphase material, wherein the polymer interphase material forms the surface layer of the mold compound having an adhesion strength to the seed layer greater than the monomer epoxy resin and hardener alone.

Abstract translation: 该文献尤其讨论了一种微电子系统，该微电子系统包括在基层上具有基层和表面层的模塑复合物，以及沉积在模塑复合物的表面层上的晶种层。 所述模塑料包括单体环氧树脂，硬化剂，填充材料和聚合物中间相材料，其中所述聚合物中间层材料形成比所述单体环氧树脂更大的与所述种子层的粘合强度的所述模塑料的表面层，以及 单独的硬化剂。

公开(公告)号：WO2017087069A1

公开(公告)日：2017-05-26

申请号：PCT/US2016/053400

申请日：2016-09-23

Applicant: INTEL CORPORATION

Inventor： ALEKSOV, Aleksandar ,  PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N.

IPC: H04M1/02 ,  H01Q1/24

CPC classification number: H05K1/184 ,  H05K1/0283 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/185 ,  H05K3/007 ,  H05K3/4697 ,  H05K2201/0133 ,  H05K2201/09263 ,  H05K2203/0191 ,  H05K2203/1469

Abstract: An embedded electronic package includes a stretchable body that includes at least one electronic component, wherein each electronic component includes a back side that is exposed from the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components. In some forms, the embedded electronic package includes a stretchable body that includes an upper surface and a lower surface, wherein the stretchable body includes at least one electronic component, wherein each electronic component is fully embedded in the stretchable body and the same distance from the upper surface of the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components.

Abstract translation: 嵌入式电子组件包括：包括至少一个电子部件的可拉伸体，其中每个电子部件包括从可拉伸体暴露的后侧; 以及电连接到一个或多个电子部件的多个曲折导体。 在一些形式中，嵌入式电子组件包括包括上表面和下表面的可拉伸主体，其中，可拉伸主体包括至少一个电子部件，其中每个电子部件完全嵌入可拉伸主​​体中，并且距离 伸缩体的上表面; 以及电连接到一个或多个电子部件的多个曲折导体。

公开(公告)号：WO2023043529A1

公开(公告)日：2023-03-23

申请号：PCT/US2022/037181

申请日：2022-07-14

Applicant: INTEL CORPORATION

Inventor： COLLINS, Andrew ,  PIETAMBARAM, Srinivas V. ,  XIE, Jianyong ,  VALAVALA, Krishna Vasanth

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to bridges having a glass core, where the bridges may include one or more thick traces and one or more thin traces, where the thin traces are layered closer to a surface of the glass core, and the thick traces are layered further away from the glass core. During operation, the thin traces may be used to transmit signals between the coupled dies, and the thick traces may be used to transmit power between the coupled dies. During manufacture, the rigidity and highly planner surface of the glass core may enable thinner traces closer to the surface of the glass core to be placed with greater precision resulting in increased overall quality and robustness of transmitted signals. Other embodiments may be described and/or claimed.

公开(公告)号：WO2023038786A1

公开(公告)日：2023-03-16

申请号：PCT/US2022/041126

申请日：2022-08-22

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  MALLIK, Debendra ,  IBRAHIM, Tarik A. ,  ECTON, Jeremy ,  KARHADE, Omkar G. ,  PENMECHA, Bharat Prasad ,  LI, Xiaoqian ,  DESHPANDE, Nitin A. ,  MODI, Mitul ,  NIE, Bai

IPC: H01L25/16 ,  G02B6/12 ,  H01L23/13 ,  H01L23/15 ,  H01L23/538 ,  H01L21/52

Abstract: An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

公开(公告)号：WO2022245425A1

公开(公告)日：2022-11-24

申请号：PCT/US2022/021881

申请日：2022-03-25

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  BHARATH, Krishna ,  VADLAMANI, Sai ,  TADAYON, Pooya ,  IBRAHIM, Tarek A.

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/15 ,  H01L25/18 ,  H01L21/48

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate having a plurality of conductive through-glass vias (TGV); a magnetic core inductor including: a first conductive TGV at least partially surrounded by a magnetic material; and a second conductive TGV electrically coupled to the first TGV; a first die in a first dielectric layer, wherein the first dielectric layer is on the glass substrate; and a second die in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the second die is electrically coupled to the magnetic core inductor.

公开(公告)号：WO2022108647A1

公开(公告)日：2022-05-27

申请号：PCT/US2021/049666

申请日：2021-09-09

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  PAITAL, Sameer ,  VADLIMANI, Sai ,  MANEPALLI, Rahul N. ,  LI, Xiaoqian ,  POTHUKUCHI, Suresh V. ,  SHARAN, Sujit ,  SARKAR, Arnab ,  KARHADE, Omkar ,  DESHPANDE, Nitin ,  PRATAP, Divya ,  ECTON, Jeremy ,  MALLIK, Debendra ,  MAHAJAN, Ravindranath V. ,  ZHANG, Zhichao ,  AYGÜN, Kemal ,  NIE, Bai ,  DARMAWIKARTA, Kristof ,  JAUSSI, James E. ,  GAMBA, Jason M. ,  CASPER, Bryan K. ,  DUAN, Gang ,  INTI, Rajesh ,  MANSURI, Mozhgan ,  JADHAV, Susheel ,  BROWN, Kenneth ,  AGRAWAL, Ankar ,  DOBRIYAL, Priyanka

IPC: G02B6/42 ,  H01L31/0203 ,  H01L23/538 ,  H01L25/16

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：WO2018182595A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/024780

申请日：2017-03-29

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N. ,  AKKINEPALLY, Praneeth ,  JONES, Jesse C. ,  KANAOKA, Yosuke ,  SENEVIRATNE, Dilan

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/67

Abstract: Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.