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    CONDENSATEUR SUR CIRCUIT INTEGRE
    11.
    发明专利
    CONDENSATEUR SUR CIRCUIT INTEGRE 未知

    公开(公告)号：FR2989221A1

    公开(公告)日：2013-10-11

    申请号：FR1253209

    申请日：2012-04-06

    Applicant: ST MICROELECTRONICS SA

    Inventor： CANDELIER PHILIPPE ,  LEROUX ELISE

    IPC: H01L29/94 ,  G11C5/14 ,  H01L23/58 ,  H01L27/11

    Abstract: Condensateur sur circuit intégré, comprenant un substrat (10) comprenant une zone (12) intégrant du silicium sur isolant (SOI) (27, 28), caractérisé en ce qu'il comprend au moins un contact (37) reliant la couche (27) conductrice de silicium positionnée sur la couche isolante (28) de la zone (12) du substrat (10) à une bande (17) en matériau conducteur positionnée dans une couche (M1) au-dessus du substrat (10), apte à une liaison à un potentiel (V2), et en ce qu'il comprend au moins un autre contact (36) reliant une couche (26) conductrice positionnée sous la couche isolante (28) à une bande (16) en matériau conducteur positionnée dans une couche (M1) au-dessus du substrat (10), apte à une liaison à un autre potentiel (V1), de sorte à pouvoir former un condensateur par les deux couches conductrices (26, 27) situées de part et d'autre de la couche isolante (28) du substrat (10).

    MEMOIRE NON-VOLATILE SECURISEE
    12.
    发明专利
    MEMOIRE NON-VOLATILE SECURISEE 未知

    公开(公告)号：FR2967522A1

    公开(公告)日：2012-05-18

    申请号：FR1004417

    申请日：2010-11-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： CANDELIER PHILIPPE ,  DEDIEU LAURENT ,  LARHRIQ NOUREDDINE

    IPC: G11C11/41 ,  H03K3/356

    Abstract: L'invention concerne une mémoire non-volatile sécurisée comprenant une cellule bistable (10, 11) ayant un état d'initialisation préprogrammé, et des moyens (12, SO, S1) pour basculer l'état de la cellule en réponse à un signal de basculement (FLP). Une horloge (13) génère le signal de basculement (FLP) avec une période inférieure au temps d'acquisition d'un microscope à émission de photons.

    13.
    发明专利
    未知

    公开(公告)号：FR2896612B1

    公开(公告)日：2008-06-27

    申请号：FR0600554

    申请日：2006-01-20

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  CANDELIER PHILIPPE ,  TESSIER JEAN MARC

    IPC: G11C11/407 ,  H01L21/8247 ,  H01L27/115

    Abstract: The device has an analog core (8) with a data control block (12) controlling operating modes of a memory and including a memory refreshing algorithm for periodically reprogramming non-volatile memory cells (9) subjected to a charge loss. The block (12) comprises an algorithm for decoding and reorganizing data bits in a redundant manner. The block (12) has a multiplexer which delivers 8 successive words of 8 bits to a 64 bit register from incident 8 bit word. The bits are delivered to a coding block (14) of an error correction block (13) including a hamming type error correction code. An independent claim is also included for a method of programming a non-volatile memory device.

    14.
    发明专利
    未知

    公开(公告)号：FR2849260B1

    公开(公告)日：2005-03-11

    申请号：FR0216558

    申请日：2002-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

    IPC: G11C14/00 ,  G11C17/14 ,  G11C11/412 ,  G11C11/417

    Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

    15.
    发明专利
    未知

    公开(公告)号：FR2787911B1

    公开(公告)日：2001-11-02

    申请号：FR9816583

    申请日：1998-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： CANDELIER PHILIPPE

    IPC: G11C17/16 ,  G11C17/18 ,  G11C17/12

    Abstract: An OTP memory integrated circuit in CMOS technology, including at least two oxide capacitors forming a differential reading storage element, and a read and programming circuit in which the transistors of a first conductivity type are adapted to being used both during read cycles under a relatively low voltage and during programming cycles under a relatively high voltage.

    19.
    发明专利
    未知

    公开(公告)号：FR2875352B1

    公开(公告)日：2007-05-11

    申请号：FR0409650

    申请日：2004-09-10

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  CANDELIER PHILIPPE ,  FOURNEL RICHARD

    IPC: H03M13/05 ,  G06F11/10 ,  H03M13/09 ,  H03M13/19 ,  H03M13/35 ,  H03M13/37

    Abstract: A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

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