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    LOW-SWITCHING-NOISE OUTPUT BUFFER
    11.
    发明专利
    LOW-SWITCHING-NOISE OUTPUT BUFFER 失效

    公开(公告)号：JPH0690153A

    公开(公告)日：1994-03-29

    申请号：JP18449293

    申请日：1993-06-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MALOBERTI FRANCO ,  MARCHESI GIANMARCO ,  TORELLI GUIDO

    IPC: G11C11/417 ,  G11C7/10 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

    Abstract: PURPOSE: To switch an output node voltage by driving a capacitive load with a fast as well as low switching noise. CONSTITUTION: The gate voltage of a transistor Tr M5 is at low level, and the gate voltage of Trs M24 and M24B is at high level. An output shift period begins, when a signal CKO becomes low. A logical level of data from a memory cell is communicated to nodes C1 to 3. The node C1 turns on MX3 and turns off MX4. Since the node C2 keeps M20 on, a node G24 is maintained at a high level, the Trs M24 and M24B are turned off, and a pull-up branch does not contribute to the output current. As voltage of a node G5 increases, voltage that flows through branches M12 and M17 is reduced, voltage value is decreased, and the node 5 is charged by a current that decreases as a function of time. This realizes an output buffer which drives a capacitive load with a switching noise, and a voltage-switching method.

    14.
    发明专利
    未知

    公开(公告)号：DE60134477D1

    公开(公告)日：2008-07-31

    申请号：DE60134477

    申请日：2001-11-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  SOLTESZ DARIO ,  PIERIN ANDREA ,  TORELLI GUIDO

    IPC: G11C5/14 ,  H02M3/07

    Abstract: A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two stages consisting of an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.

    15.
    发明专利
    未知

    公开(公告)号：DE69626804T2

    公开(公告)日：2004-03-04

    申请号：DE69626804

    申请日：1996-06-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  TELECCO NICOLA ,  TORELLI GUIDO

    IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  H03K5/13

    Abstract: A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block (RC) connected to an input terminal (ATD) for memory address line transition signals. The delay block drives a counter (CONT) which feedback controls the control block through a combinational logic circuit (COMB_SCA) connected to the output terminal (OUT_RC) of the programmable delay block. A logic output circuit (COMB_OUT), connected to the output terminal of the delay block and to the counter, generates the timing signals (OUT).

    17.
    发明专利
    未知

    公开(公告)号：DE69627318D1

    公开(公告)日：2003-05-15

    申请号：DE69627318

    申请日：1996-08-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  CALLIGARIO CRISTIANO ,  MANSTRETTA ALESSANDRO ,  TORELLI GUIDO

    IPC: G11C16/02 ,  G11C11/56 ,  G11C11/00

    Abstract: In a storage device of the multi-level type, comprising a plurality of memory cells addressable through an address input (RADR,CADR), each cell being adapted for storing more than one binary information element in a MOS transistor which has a control gate, and a floating gate for storing electrons to modify the threshold voltage of the transistor, and comprising a circuit enabling a Direct Memory Access (DMA) mode for directly accessing the memory cells from outside the device, the memory cells are programmed in the direct memory access mode by controlling, from outside the device, the amount of charge stored into the floating gate of each transistor.

    19.
    发明专利
    未知

    公开(公告)号：DE69526336D1

    公开(公告)日：2002-05-16

    申请号：DE69526336

    申请日：1995-04-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  GASTALDI ROBERTO ,  TELECCO NICOLA ,  TORELLI GUIDO

    IPC: G11C11/419 ,  G11C7/06 ,  G11C11/00

    Abstract: A reading device for devices with memory cells with two branches each comprising, connected in cascade, an electronic switch (T3, T4), an active element (T1, T2) reactively connected to the active element of the other branch, between them to form a voltage amplifier. Each active element is controlled by means of a high impedance circuit element (DL, DR). A microswitch (TE) which connects the two branches together is inserted between the two active elements (1, 2).

    20.
    发明专利
    未知

    公开(公告)号：DE69229995T2

    公开(公告)日：2000-03-16

    申请号：DE69229995

    申请日：1992-06-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FLOCCHI CARLO ,  TORELLI GUIDO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/30 ,  H03F3/345 ,  H03F3/347 ,  H03F3/50

    Abstract: A voltage regulator for electrically programmable, non-volatile memory devices, having an output terminal connected to a power supply line for programming the state of at least one memory element through at least one selection circuit means (MW,MB) and comprising at least first (R1) and second (R2) resistive elements connected between first and second terminals of a voltage supply. The regulator further comprises at least a second circuit means (MWd,MBd) being the homolog of the selection circuit means for programming the memory element, said second circuit means being connected serially to the resistive elements (R1,R2) across the two terminals of the voltage supply. Also provided is at least one controlled current generator (G1,G2) connected between one of the two voltage supply terminals and a linking node to one of the resistive elements and an operational amplifier (A) whose non-inverting (+) input is connected to a linking node to at least one of the resistive elements and whose output terminal is the output terminal of the regulator.

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