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    Phase change memory device
    11.
    发明公开
    Phase change memory device 有权
    Phasenwechselspeicheranordnung

    公开(公告)号：EP1450373A1

    公开(公告)日：2004-08-25

    申请号：EP03425098.5

    申请日：2003-02-21

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Khouri, Osama ,  Resta, Claudio

    IPC: G11C11/34 ,  G11C11/56

    CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79

    Abstract: A phase change memory (20) has an array (1) formed by a plurality of cells (2), each including a memory element (3) of calcogenic material and a selection element (4) connected in series to the memory element; a plurality of address lines (11) connected to the cells; a write stage (24) and a reading stage (25) connected to the array. The write stage (24) is formed by current generators (45), which supply preset currents to the selected cells (2) so as to modify the resistance of the memory element (3). Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

    Abstract translation: 相变存储器（20）具有由多个单元（2）形成的阵列（1），每个单元包括煅烧材料的存储元件（3）和与存储元件串联连接的选择元件（4）。 连接到所述单元的多个地址线（11） 写入级（24）和与阵列连接的读取级（25）。 写入级（24）由电流发生器（45）形成，电流发生器（45）向所选择的单元（2）提供预设电流，以便改变存储元件（3）的电阻。 通过适当地偏置所选择的单元并将其中流动的电流与参考值进行比较，读取以电压进行。

    Architecture of a phase-change nonvolatile memory array
    13.
    发明公开
    Architecture of a phase-change nonvolatile memory array 有权
    建筑工人工程师协会

    公开(公告)号：EP1326254A1

    公开(公告)日：2003-07-09

    申请号：EP01830806.4

    申请日：2001-12-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando ,  Bosisio, Giorgio ,  Pellizzer, Fabio

    IPC: G11C11/34

    CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: The phase-change nonvolatile memory array (8) is formed by a plurality of memory cells (10, 10') extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines (11) extend parallel to the first direction. A plurality of word-selection lines (12) extend parallel to the second direction. Each memory cell (10, 10') includes a PCM storage element (15) and a selection transistor (16). A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line (12). A second terminal of the PCM storage element (15) is connected to a respective column-selection line (11), and a second terminal of the selection transistor (16) is connected to a reference-potential region (18) while reading and programming the memory cells (10, 10').

    Abstract translation: 相变非易失性存储器阵列（8）由在彼此正交的第一和第二方向上延伸的多个存储单元（10,10'）形成。 多个列选择线（11）平行于第一方向延伸。 多个字选择线（12）平行于第二方向延伸。 每个存储单元（10,10'）包括PCM存储元件（15）和选择晶体管（16）。 选择晶体管的第一端子连接到PCM存储元件的第一端子，并且选择晶体管的控制端子连接到相应的字选择线（12）。 PCM存储元件（15）的第二端子连接到相应的列选择线（11），并且选择晶体管（16）的第二端子连接到参考电位区域（18），同时读取和编程 存储单元（10,10'）。

    Single supply voltage, nonvolatile memory device with cascoded column decoding
    14.
    发明公开
    Single supply voltage, nonvolatile memory device with cascoded column decoding 审中-公开
    NichtflüchtigeSpeicheranordnung mit einziger Speisespannung mit Kaskode-Spaltendekodiererung

    公开(公告)号：EP1324345A1

    公开(公告)日：2003-07-02

    申请号：EP01830808.0

    申请日：2001-12-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando

    IPC: G11C16/24

    CPC classification number: G11C13/0026 ,  G11C7/22 ,  G11C13/0038 ,  G11C16/24 ,  G11C2216/22

    Abstract: A nonvolatile memory device (1') is described comprising a memory array (2), a row decoder (3) and a column decoder (4) for addressing the memory cells (7) of the memory array (2), and a biasing stage (13,19) for biasing the drain terminal of the addressed memory cell (7). The biasing stage (13,19) is coupled between the column decoder (4) and the memory array (2) and comprises a biasing transistor (13) having a drain terminal connected to the column decoder (4), a source terminal connected to the drain terminal of the addressed memory cell (7), and a gate terminal receiving a driving signal of a logic type, the logic levels whereof are defined by precise and stable voltages and are generated by a first driving circuit (19) formed by a driving stage (20) and a buffer (21), cascade-connected.

    Abstract translation: 描述了一种非易失性存储器件（1'），其包括用于寻址存储器阵列（2）的存储器单元（7）的存储器阵列（2），行解码器（3）和列解码器（4） （13,19），用于偏置寻址的存储单元（7）的漏极端子。 偏置级（13,19）耦合在列解码器（4）和存储器阵列（2）之间，并且包括偏置晶体管（13），其漏极端子连接到列解码器（4），源极端子连接到 所述寻址的存储单元（7）的漏极端子和接收逻辑类型的驱动信号的栅极端子，其逻辑电平由精确和稳定的电压限定，并由由第一驱动电路（19）形成的第一驱动电路 驱动级（20）和缓冲器（21），级联。

    An improved page buffer for a programmable memory device
    17.
    发明公开
    An improved page buffer for a programmable memory device 有权
    一种改进的可编程存储器设备的页面缓冲区

    公开(公告)号：EP1598831A1

    公开(公告)日：2005-11-23

    申请号：EP04102232.8

    申请日：2004-05-20

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Khouri, Osama ,  Zanardi, Stefano ,  Martinozzi, Giulio

    IPC: G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/26

    Abstract: A page buffer ( 130 ) for an electrically programmable memory including a plurality of memory cells ( 110 ) forming a plurality of memory pages, the page buffer comprising at least one register ( 130m,130c ) for at least temporarily storing data read from or to be written into the memory cells of a selected memory page of said plurality, the at least one register comprising a plurality of latches ( 230m ), each latch being operatively associated with at least one respective signal line ( BLe,BLo,I/O-LINE ) transporting the data bit temporarily stored in the latch. A buffer element ( BUF ) is provided for decoupling an output of the latch from the respective signal line, the latch using the respective buffer element for driving the signal line according to the data bit stored therein.

    Abstract translation: 一种用于电可编程存储器的页缓冲器（130），所述电可编程存储器包括形成多个存储器页的多个存储器单元（110），所述页缓冲器包括至少一个寄存器（130m，130c），用于至少暂时存储从或者到 被写入所述多个选定存储页中的存储单元，所述至少一个寄存器包括多个锁存器（230m），每个锁存器与至少一个相应信号线（BLe，BLo，I / O- LINE）传输临时存储在锁存器中的数据位。 提供缓冲器元件（BUF），用于将锁存器的输出与相应的信号线去耦，锁存器使用相应的缓冲器元件根据存储在其中的数据位来驱动信号线。

    Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations
    18.
    发明公开
    Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations 有权
    非易失性的相变存储器的单电源电压，共源共栅列选择和同时读取和写入操作Wortlese-

    公开(公告)号：EP1326258A3

    公开(公告)日：2004-10-13

    申请号：EP02028616.7

    申请日：2002-12-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando

    IPC: G11C16/24 ,  G11C16/02

    CPC classification number: G11C11/5678 ,  G11C7/04 ,  G11C7/22 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2216/22

    Abstract: A nonvolatile memory device (10'; 10") is described comprising a memory array (11), a row decoder (12) and a column selector (13) for addressing the memory cells (16) of the memory array (11), and a biasing stage (22; 36, 28) for biasing the array access device terminal of the addressed memory cell (16). The biasing stage (22; 36 28) is arranged between the column selector (13) and the memory array (11) and comprises a biasing transistor (22; 36) having a drain terminal connected to the column selector (13), a source terminal connected to the array access device terminal of the addressed memory cell (16), and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block (31) and an output buffer (32) cascaded together. The output buffer (32) may be supplied with either a read voltage (VREAD) or a program voltage (VPROG) supplied by a multiplexer (33). The biasing transistor (22; 36) may be either included as part of the column selector (13) and formed by the selection transistor (22) which is closest to the addressed memory cell (16) or distinct from the selection transistors (20, 21, 22) of the column selector (13).

    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device
    20.
    发明公开
    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device 有权
    在非易失性更通常高密度存储器和相关联的换能器为模拟/数字转换的方法

    公开(公告)号：EP1211812A3

    公开(公告)日：2003-02-12

    申请号：EP00127649.2

    申请日：2000-11-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Khouri, Osama ,  Pierin, Andrea ,  Gregori, Stefano ,  Torelli, Guido

    IPC: H03M1/14 ,  G11C11/56

    CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

    Abstract: The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg). The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB). The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.

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