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    Vertical MOS device and method of making the same
    11.
    发明公开
    Vertical MOS device and method of making the same 审中-公开
    Vertikale MOS-Anordnung und Verfahren zu deren Herstellung

    公开(公告)号：EP1455397A2

    公开(公告)日：2004-09-08

    申请号：EP03029916.8

    申请日：2003-12-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Magri', Angelo ,  Frisina, Feruccio ,  Ferla, Giuseppe ,  Camalleri, Marco

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/336

    CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66712

    Abstract: The invention relates to a vertical-conduction and planar-structure MOS device having a double thickness of gate oxide comprising

    a first portion (5a) of gate oxide having a lower thickness in a channel area close to the active areas (4), and a second portion (5b) of thicker gate oxide in a central area (11) on a JFET area and
    an enrichment region (9) in the JFET area under the second . portion (5b) of thicker gate oxide (11).

    The invention also relates to a method for realising on a semiconductor substrate (2) MOS transistor electronic devices (1) with improved static and dynamic performances and high scaling down density, these transistors having traditional active areas (4) defined in the substrate (2) at the periphery of a channel region whereon a gate region is realised. The method provides at least the following steps:

    realising the MOS transistor starting from a planar structure with a double thickness of gate oxide comprising a thin layer in the channel area close to the active areas (4) and a thicker layer in the central area (11) on the channel; and
    realising an enrichment region (9) in the JFET area below the thicker layer.

    Abstract translation: 本发明涉及一种垂直导电和平面结构MOS器件，其具有栅极氧化物的双重厚度，其包括在接近有源区（4）的沟道区中具有较低厚度的栅极氧化物的第一部分（5a） 在JFET区域上的中心区域（11）中较厚的栅极氧化物的第二部分（5b）和第二部分的JFET区域中的富集区域（9）。 较厚栅极氧化物（11）的部分（5b）。 本发明还涉及一种在具有改进的静态和动态性能以及高缩小密度的半导体衬底（2）MOS晶体管电子器件（1）上实现的方法，这些晶体管具有传统的有源区域（4） 在实现栅极区域的沟道区域的周围的衬底（2）。 该方法至少提供以下步骤：从具有双重厚度的栅极氧化物的平面结构开始实现MOS晶体管，该栅极氧化物在靠近有源区域（4）的沟道区域中具有薄层，并且在中心区域中具有较厚层（ 11）在频道上 并且在较厚层下面的JFET区域中实现富集区域（9）。

    Power MOS transistor
    12.
    发明公开
    Power MOS transistor 审中-公开
    MOS-Leistungstransistor

    公开(公告)号：EP1058316A1

    公开(公告)日：2000-12-06

    申请号：EP99830343.2

    申请日：1999-06-04

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fragapane, Leonardo ,  Magri', Angelo

    IPC: H01L29/739 ,  H01L29/78 ,  H01L29/08 ,  H01L21/331 ,  H01L21/336

    CPC classification number: H01L29/7802 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/7395

    Abstract: A MOS power device such as a power MOSFET (eg. VDMOS) or an insulated gate bipolar transistor (ie. IGBT) with a high dynamic ruggedness, which comprises a parasitic bipolar transistor having its base in a base region (3,5) of the power device and means for counter-biasing the parasitic bipolar transistor. The counter-biasing means are resistive means inserted between a source region (4) of the power device and an emitter (E1) of the parasitic bipolar transistor (NPN). Said resistive means may consist of a lightly doped region (12) of the same conductivity type as that of the source region (4) of the power device and disposed in the base region (3,5) of the power device, under said source region (4).

    Abstract translation: 诸如功率MOSFET（例如VDMOS）或具有高动态耐用性的绝缘栅双极晶体管（即，IGBT）的MOS功率器件，其包括其基极在基极区域（3,5）中的基极的寄生双极晶体管 功率器件和用于对寄生双极晶体管进行反偏置的装置。 反偏置装置是插入在功率器件的源极区（4）和寄生双极晶体管（NPN）的发射极（E1）之间的电阻性装置。 所述电阻装置可以由与功率器件的源极区域（4）相同导电类型的轻掺杂区域（12）组成，并且设置在功率器件的基极区域（3,5）内，在所述源极 区域（4）。

    Power field effect transistor and manufacturing method thereof
    15.
    发明公开
    Power field effect transistor and manufacturing method thereof 审中-公开
    Leistungsfeldeffekttransistor和Verfahren zu seiner Herstellung

    公开(公告)号：EP1742271A1

    公开(公告)日：2007-01-10

    申请号：EP05425491.7

    申请日：2005-07-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Frisina, Ferruccio ,  Saggio, Mario Giuseppe ,  Magri', Angelo

    IPC: H01L29/78 ,  H01L29/10 ,  H01L21/336 ,  H01L29/423

    CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L21/047 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/6653 ,  H01L29/7835

    Abstract: Method for manufacturing electronic devices on a semiconductor substrate (1,1a;10,11) with wide band gap comprising the steps of:
    - forming a screening structure (3a,20) on said semiconductor substrate (1,1a;10,11) comprising at least a dielectric layer (2,20) which leaves a plurality of areas of said semiconductor substrate (1,1a;10,11) exposed,
    - carrying out at least a ion implantation of a first type of dopant in said semiconductor substrate (1,1a;10,11) to form at least a first implanted region (4,40),
    carrying out at least a ion implantation of a second type of dopant in said semiconductor substrate (1,1a;10,11) to form at least a second implanted region (6,6c;60,61) inside said at least a first implanted region (4,40),
    - carrying out an activation thermal process of the first type and second type of dopant with low thermal budget suitable to complete said formation of said at least first and second implanted regions (4,40;6,60).

    Abstract translation: 一种在具有宽带隙的半导体衬底（1,1a; 10,11）上制造电子器件的方法，包括以下步骤： - 在所述半导体衬底（1,1a; 10,11）上形成屏蔽结构（3a，20） 至少包括留下所述半导体衬底（1,1a; 10,11）的多个区域的电介质层（2,20），至少在所述半导体衬底中执行第一类型的掺杂剂的离子注入 （1,1a; 10,11）以形成至少第一注入区域（4,40），在所述半导体衬底（1,1a; 10,11）中至少执行第二类型掺杂剂的离子注入至 在所述至少第一注入区域（4,40）内形成至少第二注入区域（6,6c; 60,61）， - 以低热预算执行所述第一类型和第二类型掺杂剂的激活热处理 适于完成所述至少第一和第二注入区域（4,40; 6,60）的所述形成。

    Power MOS semiconductor device
    16.
    发明公开
    Power MOS semiconductor device 有权
    MOS-Leistungshalbleiteranordnung

    公开(公告)号：EP1659636A1

    公开(公告)日：2006-05-24

    申请号：EP05025285.7

    申请日：2005-11-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ferruccio, Frisina ,  Ferla, Giuseppe ,  Magri', Angelo ,  Grimaldi, Antonio Giuseppe ,  Bazzano, Gaetano

    IPC: H01L29/78 ,  H01L29/49

    CPC classification number: H01L29/7802 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4983

    Abstract: Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors (2) and a gate structure (12) comprising a plurality of conductive strips (8) realised with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks (11) connected to a gate pad (30) and at least a connection layer (20) arranged in series to at least one of said conductive strip (8). Such gate structure (12) comprising at least a plurality of independent islands (10) formed on the upper surface (9) of the conductive strips (8) and suitably formed on the connection layers (20). Said islands (10) being realised with at least one second conductive material such as silicide.

    Abstract translation: 包括多个基本功率MOS晶体管（2）和栅极结构（12）的功率电子MOS器件包括由诸如多晶硅的第一导电材料实现的多个导电条（8），多个栅极指或者 连接到栅极焊盘（30）的金属轨道（11）和至少与所述导电条（8）中的至少一个串联布置的连接层（20）。 这种栅极结构（12）包括形成在导电条（8）的上表面（9）上并适当地形成在连接层（20）上的至少多个独立的岛（10）。 所述岛（10）用至少一种第二导电材料（例如硅化物）实现。

    Single feature size MOS technology power device
    17.
    发明授权
    Single feature size MOS technology power device 失效
    在MOS技术的电力设备与单一的克里提卡尔·马斯

    公开(公告)号：EP0772242B1

    公开(公告)日：2006-04-05

    申请号：EP95830454.5

    申请日：1995-10-30

    Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

    Inventor： Frisina, Ferruccio ,  Magri', Angelo ,  Ferla, Giuseppe

    IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739 ,  H01L21/331

    CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/66333

    Abstract: A MOS technology power device comprises: a semiconductor material layer (2) of a first conductivity type; a conductive insulated gate layer (7,8,9) covering the semiconductor material layer (2); a plurality of elementary functional units, each elementary functional unit comprising a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of an elongated body stripe, each elementary functional unit further comprising an elongated window (12) in the insulated gate layer (7,8,9) extending above the elongated body stripe (3). Each body stripe (3) includes at least one source portion (60;61;62) doped with dopants of the first conductivity type, intercalated with a body portion (40;41;3') of the body stripe (3) wherein no dopant of the first conductivity type are provided. The conductive insulated gate layer (7,8,9) comprises a first insulating material layer (7) placed above the semiconductor material layer (2), a conductive material layer (8) placed above the first insulating material layer (7), and a second insulating material layer (9) placed above the conductive material layer (8). Insulating material sidewall spacers (13) are provided to seal edges of the elongated window (12) in the insulated gate layer (7,8,9).

    MOS power device with high integration density and manufacturing process thereof
    18.
    发明公开
    MOS power device with high integration density and manufacturing process thereof 审中-公开
    MOS-Leistungsbauelement mit hoher Integrationsdichte und dessen Herstellungsverfahren

    公开(公告)号：EP1450411A1

    公开(公告)日：2004-08-25

    申请号：EP03425099.3

    申请日：2003-02-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Frisina, Ferruccio ,  Ferla, Giuseppe ,  Magri', Angelo ,  Salinas, Dario

    IPC: H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/66712

    Abstract: A MOS power device having: a body (10); gate regions (34) on top of the body (10) and delimiting therebetween a window (40); a body region (35), extending in the body underneath the window; a source region (36), extending inside the body region (35) throughout the width of the window; body contact regions (43), extending through the source region up to the body region; source contact regions (46), extending inside the source region, at the sides of the body contact regions; a dielectric region (41) on top of the source region; openings (42, 45) traversing the dielectric region on top of the body and source contact regions (43, 46); and a metal region (50) extending above the dielectric region (41) and through the first and second openings (42, 45).

    Abstract translation: 一种MOS功率器件，具有：主体（10）; 门区域（34）在主体（10）的顶部上并在其间界定窗口（40）; 身体区域（35），其在所述窗户下方的身体中延伸; 源区域（36），其在所述窗体的整个宽度内在所述体区域（35）内延伸; 身体接触区域（43），延伸穿过源区域直到身体区域; 源极接触区域（46），其在源极区域内延伸，位于身体接触区域的侧面; 在所述源极区域的顶部上的电介质区域（41） 穿过主体顶部的电介质区域和源极接触区域（43,46）的开口（42,45）; 以及在所述电介质区域（41）上方延伸并且穿过所述第一和第二开口（42,45）的金属区域（50）。

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