公开(公告)号：JP2012174874A

公开(公告)日：2012-09-10

申请号：JP2011035113

申请日：2011-02-21

Applicant: Fujitsu Ltd ,  富士通株式会社

Inventor： YOSHIMURA HIDEAKI

IPC: H05K3/44 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/445 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4608 ,  H05K2201/029 ,  H05K2201/0293 ,  H05K2201/0323 ,  H05K2201/09636 ,  Y10T29/49165

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a printed wiring board which prevents drooping when a lower hole is filled with an insulation material.SOLUTION: In a manufacturing method of a printed wiring board, a process where a lower hole 3 is formed on a surface part of a conductive base material 2 having a low thermal expansion coefficent and a process where a peeling film 12 is bonded to the surface part 2c of the base material 2 on a bottom surface side of the lower hole 3, thereby forming a bottom part 8 closing the bottom surface side of the lower hole 3 with the bonded film 12 are conducted. Further, in the manufacturing method, a process that the lower hole 3 is filled with an insulation material 4 and a process where multiple through holes 5 are formed in the lower hole 3 filled with the insulation material 4 are conducted.

Abstract translation: 要解决的问题：提供一种当下部孔填充有绝缘材料时防止下垂的印刷线路板的制造方法。 解决方案：在印刷电路板的制造方法中，在具有低热膨胀系数的导电性基材2的表面部分和形成剥离膜12的工序中形成下孔3的工序 在底孔3的底面侧的基材2的表面部分2c上形成底部8，该底部8用接合膜12封闭下孔3的底面侧。 此外，在制造方法中，进行了填充绝缘材料4的下部孔3的填充处理和在填充有绝缘材料4的下部孔3中形成有多个通孔5的工序。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2011211155A

公开(公告)日：2011-10-20

申请号：JP2010231660

申请日：2010-10-14

Applicant: Panasonic Corp ,  パナソニック株式会社

Inventor： KITANO NAOFUMI ,  NISHIMURA TOSHIRO

IPC: H05K3/46 ,  H01L23/12

CPC classification number: H05K1/0231 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/165 ,  H05K3/4614 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: PROBLEM TO BE SOLVED: To provide an electronic circuit including an integrated circuit as a noise source, a bypass capacitor, and a circuit board having them mounted thereon, and suppressing a noise radiation level.SOLUTION: The electronic circuit has the integrated circuit 1, the bypass capacitor 7, and the circuit board 3 having the integrated circuit 1 and the bypass capacitor 7, mounted thereon. In the electronic circuit, one electrode terminal 8a of the bypass capacitor 7 and one connecting electrode 2a of the integrated circuit 1 are connected through a first connection wiring 4a formed on the circuit board 3, and, additionally, another electrode terminal 8b of the bypass capacitor 7 and another connecting electrode 2b of the integrated circuit 1 are connected through a second connection wiring 4b formed on the circuit board 3, and a gap between the first connection wiring 4a and the second connection wiring 4b is made smaller than either a gap between the connecting electrodes 2a, 2b on the integrated circuit 1, or a gap between the electrode terminals 8a, 8b of the bypass capacitor 7.

Abstract translation: 要解决的问题：提供一种电子电路，其包括作为噪声源的集成电路，旁路电容器和安装在其上的电路板，并且抑制噪声辐射水平。解决方案：电子电路具有集成电路1， 旁路电容器7和具有集成电路1和旁路电容器7的电路板3安装在其上。 在电子电路中，旁路电容器7的一个电极端子8a和集成电路1的一个连接电极2a通过形成在电路板3上的第一连接配线4a连接，另外还有旁路的另一个电极端子8b 电容器7和集成电路1的另一个连接电极2b通过形成在电路板3上的第二连接线4b连接，第一连接配线4a和第二连接配线4b之间的间隙小于 集成电路1上的连接电极2a，2b，或旁路电容器7的电极端子8a，8b之间的间隙。

公开(公告)号：JP2011521439A

公开(公告)日：2011-07-21

申请号：JP2010546970

申请日：2008-05-26

Applicant: 日本電気株式会社

Inventor： タラス クシュタ ,  光 古宇田 ,  淳 堺

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0245 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: 多層基板が、複数の導電性プレーンが設けられた導電性プレーン領域と、前記導電性プレーンが排除されるように、前記導電性プレーン領域に隣接して設けられた隔離領域とを備えている。 複数の信号ビアが、前記複数の導電性プレーンから絶縁されるように、前記隔離領域を通過して設けられる。 導電体ポストが、前記複数の導電性プレーンの一に接続され、前記隔離領域の前記信号ビアの２つの間の領域に延伸するように設けられている。

公开(公告)号：JP2007274471A

公开(公告)日：2007-10-18

申请号：JP2006099064

申请日：2006-03-31

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： IWATA TADASHI

IPC: H03H7/38 ,  H03H7/46 ,  H03H9/72 ,  H04B1/3822 ,  H04B1/40 ,  H05K3/46

CPC classification number: H05K1/0243 ,  H03H7/463 ,  H03H9/725 ,  H03H2001/0085 ,  H04B1/0057 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/1003 ,  H05K2201/10083

Abstract: PROBLEM TO BE SOLVED: To suppress inductance in signal transmission paths of a high-frequency module which is provided with a laminated substrate and includes the signal transmission paths interconnecting several circuit elements and terminals. SOLUTION: The high-frequency module 1 is provided with the laminated substrate 200. The laminated substrate 200 has a bottom 200a and a top 200b. A terminal Rx11 is arranged on the bottom 200a. A SAW filter 121 and an inductor 81 are mounted on the top 200b. The laminated substrate 200 has a conductor layer 433 which connects the SAW filter 121 and the inductor 81, a conductor layer 451 which is arranged at a position nearer to the bottom 200a than to the conductor layer 433 and is connected with the terminal Rx11 and several parallel signal paths 701 and 702, each of which is constituted of at least one through-hole provided in the laminated substrate 200, and which connect the conductor layer 433 and the conductor layer 451. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了抑制设置有层叠基板的高频模块的信号传输路径中的电感，并且包括互连多个电路元件和端子的信号传输路径。 解决方案：高频模块1设置有层叠基板200.层叠基板200具有底部200a和顶部200b。 端子Rx11布置在底部200a上。 SAW滤波器121和电感器81安装在顶部200b上。 层叠基板200具有连接SAW滤波器121和电感器81的导体层433，布置在比导体层433更靠近底部200a的位置并与端子Rx11连接的多个导体层451 平行信号路径701和702，每个由至少一个设置在层叠基板200中的通孔构成，并且连接导体层433和导体层451.版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007250645A

公开(公告)日：2007-09-27

申请号：JP2006069174

申请日：2006-03-14

Applicant: Daikin Ind Ltd ,  ダイキン工業株式会社

Inventor： OKANO TAKASHI

IPC: H05K3/46

CPC classification number: H05K1/0216 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H05K1/0219 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09636 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To reduce noise generated by a return current flowing in a multilayered substrate.
SOLUTION: The substrate includes: an insulating substrate 2; two sets of wiring 311, 312; signal lines 321, 322, 331 and 332; and vias 323, 333, 341 and 342. Two sets of wiring 311, 312 are laminated in a prescribed direction 90 via an insulating board 202 of a part of the insulating substrate 2 between surfaces 21a, 21b. The signal lines 321, 331 are arranged on the surface 21a so as to face the wiring 311. The signal lines 322, 332 are arranged on the surface 21b so as to face the wiring 312. The via 323 connects the signal lines 321, 322. The via 333 connects the signal lines 331, 332. The vias 341, 342 are arranged on the insulating board 202 so as to connect two sets of wiring 311, 312. The via 341 is arranged close to the via 323, and the via 342 is arranged close to the via 333.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：减少在多层基板中流动的回流产生的噪声。 解决方案：基板包括：绝缘基板2; 两组接线311,312; 信号线321,322,331和332; 和通孔323,333,341,342。两组布线311,312经由表面21a，21b之间的绝缘基板2的一部分的绝缘板202沿规定方向90层压。 信号线321,331被布置在表面21a上以与布线311相对。信号线322,332布置在表面21b上以面对布线312。通孔323将信号线321,322 通孔333连接信号线331,332。通孔341,342布置在绝缘板202上，以便连接两组布线311,312。通孔341布置成靠近通孔323，并且通孔 342靠近通道333安排。版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004327690A

公开(公告)日：2004-11-18

申请号：JP2003119960

申请日：2003-04-24

Applicant: Fuji Xerox Co Ltd ,  富士ゼロックス株式会社

Inventor： IGUCHI DAISUKE

IPC: H05K3/46 ,  H01L23/12 ,  H05K1/02 ,  H05K1/11 ,  H05K1/16 ,  H05K3/34 ,  H05K3/42

CPC classification number: H05K1/0251 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/12042 ,  H05K1/0222 ,  H05K1/0231 ,  H05K1/0245 ,  H05K1/115 ,  H05K1/162 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/0949 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09809 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To provide a printed circuit board at low cost which can be applied to a circuit board wherein a base lock operates at a high speed of 1GHz or more, and can suppress electromagnetic radiation, such as common mode radiation. SOLUTION: The printed circuit board 10 has an arrangement wherein a first signal wiring layer 12, a first ground layer 14, a second ground layer 16 and a second signal wiring layer 18 are stacked through an insulating member 20 with a first through hole 100 being provided therethrough. First signal wiring 102 is formed in the first signal wiring layer 12, and second signal wiring 104 is formed in the second signal wiring layer 18 with the signal wiring 102 and the signal wiring 104 being connected through the through hole 100. The conductive first ground layer 14 and the second ground layer 16 are connected through a second through hole 106. The second through hole 106 is formed so as to be insulated from the first through hole 100, and to surround the first through hole 100. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 解决的问题：为了提供低成本的印刷电路板，其可以应用于电路板，其中基座锁以1GHz或更高的速度操作，并且可以抑制诸如共模辐射的电磁辐射 。 解决方案：印刷电路板10具有第一信号布线层12，第一接地层14，第二接地层16和第二信号布线层18通过绝缘构件20堆叠的布置，第一通孔 孔100设置在其中。 第一信号布线102形成在第一信号布线层12中，第二信号布线104形成在第二信号布线层18中，信号布线102和信号布线104通过通孔100连接。导电的第一地 层14和第二接地层16通过第二通孔106连接。第二通孔106形成为与第一通孔100绝缘，并且围绕第一通孔100。版权所有： （C）2005，JPO＆NCIPI

公开(公告)号：US11792916B2

公开(公告)日：2023-10-17

申请号：US17567332

申请日：2022-01-03

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Han Park ,  Woo Seok Yang

IPC: H05K1/02 ,  H05K3/10 ,  H05K1/11

CPC classification number: H05K1/0224 ,  H05K1/116 ,  H05K3/107 ,  H05K2201/09036 ,  H05K2201/09636

Abstract: A printed circuit board includes an insulating layer; a recess portion disposed on one surface of the insulating layer; and a circuit layer disposed on the one surface of the insulating layer and including a signal pattern and a ground pattern. At least a portion of the ground pattern covers at least a portion of the recess portion.

公开(公告)号：US20230319997A1

公开(公告)日：2023-10-05

申请号：US17710944

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Aslam HASWAREY ,  Anne AUGUSTINE ,  Yan Fen SHEN

IPC: H05K1/16 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/0094 ,  H05K2201/09636 ,  H05K2201/0959 ,  H05K2201/09563 ,  H05K1/181

Abstract: Embodiments herein relate to systems, apparatuses, or processes to using vias, or plated through holes (PTH), within a substrate or within a sub laminate to create capacitors. The interior of a via may have a first layer, or coating, of an electrically conductive material such as copper, formed on the sides of the via. A second layer including a dielectric material is placed on the first layer of the electrically conductive material. A third layer of electrically conductive material may then be placed on the second layer of the dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US11758644B2

公开(公告)日：2023-09-12

申请号：US17319577

申请日：2021-05-13

Applicant: Dell Products L.P.

Inventor： Jason Pritchard ,  Charles W. Ziegler, IV ,  Qianwen Wang ,  Lingyu Kong

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0222 ,  H05K2201/09618 ,  H05K2201/09636

Abstract: A circuit board may include a traditional via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board and a slotted via formed within the circuit board proximate to the traditional via, the slotted via comprising an opening through a first surface and a second surface of the circuit board and a layer of conductive material formed on interior walls of the opening.

公开(公告)号：US11751323B2

公开(公告)日：2023-09-05

申请号：US17443742

申请日：2021-07-27

Applicant: DELL PRODUCTS, LP

Inventor： Sandor Farkas ,  Bhyrav Mutnury

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0245 ,  H05K1/115 ,  H05K3/4644 ,  H05K1/18 ,  H05K2201/09636 ,  H05K2201/09672

Abstract: A printed circuit board (PCB) is provided for transmitting a differential signal. The PCB includes first and second conductive signal layers. The first conductive signal layer includes a first positive trace of the differential signal and a first negative trace of the differential signal. The second conductive signal layer includes a second positive trace of the differential signal and a second negative trace of the differential signal. The first positive trace is adjacent to the first negative trace, and the second positive trace is adjacent to the second negative trace and directly below the first negative trace.