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公开(公告)号：KR101102671B1
公开(公告)日：2012-01-05
申请号：KR1020100045681
申请日：2010-05-14
Applicant: 국민대학교산학협력단
IPC: H01L27/108 , H01L21/8242
Abstract: 본 발명은 커패시터가 없는 SBE 디램 셀 트랜지스터에 관한 것으로서, 보다 구체적으로는 충돌 이온화(Impact Ionization)에 의해 생성되는 홀이 빠져나가는 것을 물리적으로 방해하기 위하여 형성된 이산화실리콘(SiO
2 ) 장벽; 이산화실리콘 장벽의 상단에 형성되는 한 쌍의 실리콘(Si) 소스/드레인 층; 상기 이산화실리콘(SiO
2 ) 장벽에 둘러싸이며, 상기 한 쌍의 실리콘 소스/드레인 층 사이에 인접하여 형성되는, 결정구조의 실리콘(Si) 채널 층; 및 상기 실리콘 채널 층 하단에 이종 접합되며 충돌 이온화에 의해 생성되는 홀을 저장하는 실리콘저마늄(SiGe)층을 포함하는 것을 그 구성상의 특징으로 한다.
본 발명에서 제안하고 있는 커패시터가 없는 SBE 디램 셀 트랜지스터에 따르면, 실리콘 채널 아래에 있는 실리콘저마늄 층이, 실리콘 층과 실리콘저마늄 층 사이의 밴드 오프셋을 이용하여 홀을 가둠으로써 전하 유지 특성을 향상시킬 수 있다.
또한, 반복된 실리콘/실리콘저마늄 구조를 통하여 격자의 불일치로 인한 결함을 줄일 수 있으며, 이산화실리콘으로 만들어진 물리적인 장벽이 홀의 저장 공간과 소스/드레인을 분리시켜 데이터 '1'의 쓰기 동작 동안 생성된 홀들이 빠져 버리는 것과 홀을 저장하는 실리콘저마늄층에서의 SRH 재결합이 발생하는 것 모두를 차단할 수 있다.
뿐만 아니라, 상부 게이트 워드 라인과 하부 게이트 워드 라인을 다른 금속 층으로 구성하고, 셀 배열에서 소스를 한 개의 비트 라인으로 공유하여 결과적으로 셀의 최소 배선 폭을 줄여 4F
2 의 셀 크기를 얻을 수 있다.-
公开(公告)号：KR100942240B1
公开(公告)日：2010-02-16
申请号：KR1020090064183
申请日：2009-07-14
Applicant: 국민대학교산학협력단
IPC: H01L27/115 , G11C16/04
CPC classification number: H01L29/7855 , H01L21/28282 , G11C16/04 , H01L21/265 , H01L21/31051
Abstract: PURPOSE: A multi-bit-per cell non-volatile memory cell and a method of operating for the multi-bits cell operation are provided to perform in rapidly at a lower voltage while a recording and erasing operation by using reading a gate induced drain leakage. CONSTITUTION: An active pin for a source and a drain region is patterned at the both sides of a silicon substrate by using a hard mask pattern with a mask. An oxide film is deposited after removing the hard mask pattern. The first oxide film is formed at the active area for resource and drain region. A poly-silicon is deposited. T-shape gate is patterned by using a deposited poly-silicon with the hard mask. A second oxide film is formed on a gate region of T-shape.
Abstract translation: 目的：提供一个多位单元非易失性存储单元和一种操作多位单元操作的方法，以在较低电压下快速执行，同时通过读取栅极感应漏极泄漏进行记录和擦除操作 。 构成：通过使用具有掩模的硬掩模图案，在硅衬底的两侧上对源极和漏极区域的有源引脚进行构图。 去除硬掩模图案后，沉积氧化膜。 第一氧化物膜形成在用于资源和漏极区域的有源区域。 沉积多晶硅。 通过使用具有硬掩模的沉积的多晶硅来对T形栅极进行图案化。 在T形的栅极区域上形成第二氧化膜。
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23.发明授权
公开(公告)号：KR101557935B1
公开(公告)日：2015-10-08
申请号：KR1020140188932
申请日：2014-12-24
Applicant: 국민대학교산학협력단
IPC: H01L21/66
CPC classification number: H01L22/12
Abstract: 본발명은다결정박막트랜지스터에서결정립경계가존재하지않는경우의커패시턴스-전압특성과결정립경계가존재하는경우의커패시턴스-전압특성의차를이용하여결정립경계의위치에의존하여변하는공핍커패시턴스를통해유효한공핍영역의폭을구해최종적으로는결정립경계의위치를추출하는장치및 방법을제공하기위한것으로서, 결정립경계가채널내에존재하는소자의커패시턴스-전압특성을검출하는 C-V특성검출부와, 상기검출된커패시턴스-전압특성을기반으로공핍영역을형성할수 있는크기에해당하는게이트전압이인가되었을경우의커패시턴스값을추출하는커패시턴스값 추출부와, 상기추출된커패시턴스값으로부터결정립경계의위치에의존하여변하는공핍커패시턴스를분리추출하는공핍커패시턴스추출부와, 상기분리추출된공핍커패시턴스로부터유효한공핍영역의폭을산출하여공핍층의두께로부터결정립경계의수직방향위치를산출하는결정립계위치산출부를포함하여구성되는데있다.
Abstract translation: 本发明是提供一种通过利用晶界的位置变化的耗尽电容获得有效耗尽区的宽度来提取晶界位置的装置和方法，其使用电容 - 电压特性 在多晶薄膜晶体管中不存在晶界的情况和存在晶界的情况的电容 - 电压特性。 本发明的装置包括：C-V特性检测部，其检测在通道中存在晶界的装置的电容 - 电压特性; 电容值提取部，其根据检测出的电容电压特性，施加与能够形成耗尽区的振幅相对应的栅极电压的情况下提取电容值; 耗尽电容提取部，其根据所提取的电容值分离并提取根据晶界的位置而变化的耗尽电容; 以及晶界位置计算部分，通过从分离和提取的耗尽电容计算有效耗尽区的宽度，从耗尽区的厚度计算晶界的垂直位置。
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公开(公告)号：KR1020150081709A
公开(公告)日：2015-07-15
申请号：KR1020140001460
申请日：2014-01-06
Applicant: 국민대학교산학협력단
IPC: G01N27/416 , G01N27/327 , G01N27/414
CPC classification number: G01N27/416 , G01N27/327 , G01N27/414
Abstract: 본발명은디지털화신호처리부가집적된바이오센서및 감지방법에관한것으로, 보다상세하게는하향식(top-down approach) 제조공정을이용하여디지털화(Digitizer) 신호처리부와상호보완적인(Complementary) 바이오센서가집적된바이오센서및 바이오물질감지방법에관한것이다. 본발명에서는반도체특성을가지는나노소자의게이트전압에대한바이오물질과수용체(receptor)의반응에따른감지신호를생성하여상태변수에따라디지털화된비트(digitized bit)의테이블을측정하고, 측정된디지털레벨각각을저장하여바이오물질의감지속도를높이고, 민감도를높이는것을목적으로한다.
Abstract translation: 本发明涉及一种与数字化信号处理部分和感测方法相结合的生物传感器，更具体地说，涉及一种利用自上而下的方法处理将互补生物传感器与数字化信号处理部件集成的生物传感器， 和生物材料感测方法。 本发明能够根据状态变量通过根据受体和生物材料与具有半导体特性的纳米元件的栅极电压的反应产生感测信号来测量数字化位的表格，并且增加 通过存储每个测量的数字电平，生物材料的灵敏度和感测速度。
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公开(公告)号：KR101529704B1
公开(公告)日：2015-06-18
申请号：KR1020140009660
申请日：2014-01-27
Applicant: 국민대학교산학협력단
IPC: H01L21/66 , H01L29/786
CPC classification number: H01L22/14 , H01L22/30 , H01L29/78663
Abstract: 비정질반도체박막트랜지스터의이동도추출방법및 그장치가개시된다. 본발명의일 실시예에따른비정질반도체박막트랜지스터의이동도추출방법은상기박막트랜지스터의밴드갭내 상태밀도를획득하는단계; 상기추출된상기밴드갭내 상태밀도를이용하여문턱전압보다낮은전압영역에대한상기박막트랜지스터의제1 이동도를계산하는단계; 상기박막트랜지스터의측정된게이트전압에따른측정데이터와상기게이트전압에따른측정데이터의미리정의된수학적모델을비교하여상기문턱전압보다높은전압영역에대한상기박막트랜지스터의제2 이동도를계산하는단계; 및상기계산된상기제1 이동도와상기제2 이동도를이용하여상기박막트랜지스터의이동도를추출하는단계를포함한다.
Abstract translation: 公开了提取非晶半导体薄膜晶体管的迁移率的方法和装置。 根据本发明的实施例的提取非晶半导体薄膜晶体管的迁移率的装置包括获得薄膜晶体管的带隙中的状态密度的步骤; 通过使用所提取的状态密度来计算比阈值电压低的电压区域的薄膜晶体管的第一迁移率的步骤; 通过根据栅极电压和测量数据根据薄膜晶体管的测量栅极电压比较测量数据的预定数学模型，计算比阈值电压高的电压区域的薄膜晶体管的第二迁移率的步骤 ; 以及通过使用所计算的第一和第二迁移率来提取薄膜晶体管的迁移率的步骤。
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Patent Agency Ranking26.发明授权복수의 주파수에 대한 커패시턴스-전압 특성을 이용한 비정질 산화물 반도체 박막 트랜지스터의 밴드갭 내 상태밀도 추출 방법 및 그 장치 有权使用频率分散电容特性提取非晶氧化物半导体薄膜晶体管状态子阱密度的方法及其设备
公开(公告)号：KR101375787B1
公开(公告)日：2014-03-18
申请号：KR1020130025094
申请日：2013-03-08
Applicant: 국민대학교산학협력단
IPC: H01L21/66 , H01L29/786 , G02F1/136
CPC classification number: H01L22/12 , H01L29/78693
Abstract: Disclosed are a method for extracting the state density in a band gap of an amorphous oxide semiconductor thin film transistor, and a device therefor. The method for extracting the state density in a band gap of an amorphous oxide semiconductor thin film transistor according to an embodiment of the present invention comprises the steps of: measuring capacitance and conductance according to gate voltage relative to predetermined frequencies; calculating local capacitance formed by a local trap in a channel based on the measured capacitance and conductance; and extracting the state density in the band gap based on the calculated local capacitance. When the local capacitance is calculated, channel conductance formed at the channel is calculated using the measured capacitance and conductance. As the local capacitance is calculated based on the calculated channel conductance, entire state density in the band gap can be simply and rapidly extracted using only experimentally measured data without iteration procedures and complicated calculation. And local capacitance and free electrons capacitance can be separated quantitatively according to the gate voltage. [Reference numerals] (AA) Start; (BB) End; (S210) Measuring conductance and capacitance according to gate voltage relative to multiple frequencies; (S220) Calculating channel conductance formed at a channel by using the measured capacitance and conductance; (S230) Calculating local capacitance (C_loc) formed by a local trap in the channel based on the calculated channel conductance; (S240) Extracting state density in a band gap based on the calculated local capacitance
Abstract translation: 公开了一种用于提取非晶氧化物半导体薄膜晶体管的带隙中的状态密度的方法及其装置。 根据本发明实施例的用于提取非晶氧化物半导体薄膜晶体管的带隙中的状态密度的方法包括以下步骤：根据预定频率的栅极电压测量电容和电导; 基于测量的电容和电导计算由通道中的局部陷阱形成的局部电容; 并根据所计算的局部电容提取带隙中的状态密度。 当计算局部电容时，使用测量的电容和电导计算在通道处形成的沟道电导。 由于局部电容是根据计算出的通道电导计算的，所以可以使用实验测量数据，无需迭代程序和复杂的计算，即可简单快速地提取带隙中的整体状态密度。 局部电容和自由电子电容可根据栅极电压定量分离。 （附图标记）（AA）开始; （BB）结束; （S210）根据多个频率的栅极电压测量电导率和电容值; （S220）通过使用测量的电容和电导计算在通道处形成的通道电导; （S230）基于所计算的通道电导计算由通道中的局部陷阱形成的局部电容（C_loc）; （S240）基于计算的局部电容提取带隙中的状态密度
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27.发明授权광 미분 바디 팩터를 이용한 금속 산화물 반도체 전계 효과 트랜지스터의 밴드갭 내 상태밀도 추출 방법 및 그 장치 有权使用光学差分体因子提取金属氧化物半导体场效应晶体的子阱密度的方法及其设备
公开(公告)号：KR101375784B1
公开(公告)日：2014-03-18
申请号：KR1020130025150
申请日：2013-03-08
Applicant: 국민대학교산학협력단
IPC: H01L21/66 , H01L29/786 , G02F1/136
CPC classification number: H01L22/12 , H01L22/30 , H01L29/7869
Abstract: A method for extracting state density inside a band gap of a metal oxide semiconductor field effect transistor using an optical differential body factor and a device thereof are disclosed. The method for extracting the state density inside a band gap of a metal oxide semiconductor field effect transistor according to an embodiment of the present invention includes the steps of: measuring the drain current of a darkroom according to the gate voltage of the metal oxide semiconductor field effect transistor in the darkroom and measuring optical response drain current according to the gate voltage of the metal oxide semiconductor field effect transistor by irradiating the light of a predetermined light source; calculating a darkroom body factor according to the gate voltage using the measured darkroom drain current and calculating an optical response body factor according to the gate voltage using the measured optical response drain current; and extracting the state density inside a band gap of a metal oxide semiconductor field effect transistor based on the calculated darkroom body factor and the optical response body factor. The state density in an independent band of a threshold voltage gap can be extracted without omitting a complicated measurement process and the state density inside the band gap can be simply and rapidly extracted. [Reference numerals] (AA) Start; (BB) End; (S410) Measuring darkroom drain current according to gate voltage in a darkroom; (S420) Measuring optical response drain current according to gate voltage by radiating the light of a light source; (S430) Calculating a darkroom body factor using the darkroom drain current; (S440) Calculating the optical response body factor using the optical response drain current; (S450) Extracting the state density in the band gap based on the differentiation of the darkroom body factor and the optical response body factor
Abstract translation: 公开了一种使用光学差分体因子及其装置提取金属氧化物半导体场效应晶体管的带隙内的状态密度的方法。 根据本发明实施例的用于提取金属氧化物半导体场效应晶体管的带隙内的状态密度的方法包括以下步骤：根据金属氧化物半导体场的栅极电压测量暗室的漏极电流 并且通过照射预定光源的光来测量根据金属氧化物半导体场效应晶体管的栅极电压的光响应漏极电流; 使用测量的暗室漏极电流根据栅极电压计算暗室体因子，并使用测量的光响应漏极电流根据栅极电压计算光响应体系因子; 并且基于计算出的暗室体因子和光响应体因子，提取金属氧化物半导体场效应晶体管的带隙内的状态密度。 可以提取阈值电压间隙的独立频带中的状态密度而不省略复杂的测量过程，并且可以简单且快速地提取带隙内的状态密度。 （附图标记）（AA）开始; （BB）结束; （S410）根据暗室中的栅极电压测量暗室漏极电流; （S420）通过照射光源来测量根据栅极电压的光学响应漏极电流; （S430）使用暗室漏极电流计算暗室体系因子; （S440）使用光学响应漏极电流计算光学响应体因子; （S450）基于暗房体因子和光学响应体因子的差异提取带隙中的状态密度
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公开(公告)号：KR101126981B1
公开(公告)日：2012-03-26
申请号：KR1020110077904
申请日：2011-08-04
Applicant: 국민대학교산학협력단
IPC: H01L21/66 , H01L29/786
CPC classification number: H01L22/14 , H01L22/12 , H01L29/78663
Abstract: PURPOSE: A method for extracting a parasitic serial resistance element of an amorphous thin film transistor is provided to separate and extract various resistance elements by using structural parameters of a TFT, a current-voltage property, and a capacitance-voltage property. CONSTITUTION: A capacitance between a gate and a source of an amorphous thin film transistor and a capacitance between the gate and a drain thereof are measured(S210). A vertical resistance element is extracted among parasitic serial resistance elements(S220). Each contact resistant element and each bulk resistance element are separated and extracted(S230). A current between the drain and the source of the amorphous thin film transistor is measured(S240). A serial resistance value is extracted based on the current between the drain and the source(S250). A horizontal resistance element is extracted among the parasitic serial resistance element(S260). A transmission resistance element and a channel resistance element are separated and extracted from the horizontal resistance element(S270).
Abstract translation: 目的：提供一种用于提取非晶薄膜晶体管的寄生串联电阻元件的方法，通过使用TFT的结构参数，电流 - 电压特性和电容 - 电压特性来分离和提取各种电阻元件。 结构：测量非晶薄膜晶体管的栅极和源极之间的电容以及栅极和漏极之间的电容（S210）。 在寄生串联电阻元件中提取垂直电阻元件（S220）。 每个接触电阻元件和每个体电阻元件被分离和提取（S230）。 测量非晶薄膜晶体管的漏极和源极之间的电流（S240）。 基于漏极和源极之间的电流提取串联电阻值（S250）。 在寄生串联电阻元件中提取水平电阻元件（S260）。 从水平电阻元件分离并提取传输电阻元件和沟道电阻元件（S270）。
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