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公开(公告)号：KR1020090020739A
公开(公告)日：2009-02-27
申请号：KR1020070085268
申请日：2007-08-24
Applicant: 재단법인서울대학교산학협력재단
Inventor： 윤의준
IPC: H01L33/02
Abstract: A substrate for a semiconductor device, a manufacturing method thereof and a method of manufacturing a semiconductor device using the same are provided to omit polishing and scribing tasks of a substrate at post-processing by using a heterojunction substrate. A substrate for a semiconductor device comprises a mono crystal substrate(10) and a heterojunction substrate(20). A separation groove(15) for separating a chip area is formed in the lower-part of the mono crystal substrate. The heterojunction substrate is welded with an oxide film as intermediation in the lower-part of the mono crystal substrate and supports the mono crystal substrate. The mono crystal substrate is one among sapphire, SiC, GaAs, GaN, AlN, ZrB2, LiAlO2, MgO, spinel(MgAl2O4) ZnO and LiGaO2. The oxide film is one among a silicon oxide film(SiO2), ZrO2, Al2O3, TiO2, PSG(Phosphorous Silicate Glass) and BPSG(Boro-Phosphorous Silicate Glass).
Abstract translation: 提供半导体器件的衬底，其制造方法和使用其的半导体器件的制造方法，以通过使用异质结衬底在后处理中省略衬底的抛光和划线任务。 一种用于半导体器件的衬底包括单晶衬底（10）和异质结衬底（20）。 在单晶衬底的下部形成用于分离芯片区域的分离槽（15）。 异相结合基板与单晶基板的下部中间化合有氧化膜，并支撑单晶基板。 单晶基板是蓝宝石，SiC，GaAs，GaN，AlN，ZrB2，LiAlO2，MgO，尖晶石（MgAl2O4）ZnO和LiGaO2之一。 氧化膜是氧化硅膜（SiO 2），ZrO 2，Al 2 O 3，TiO 2，PSG（磷酸硅酸盐玻璃）和BPSG（硼 - 磷酸硅酸盐玻璃）之一。
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公开(公告)号：KR100645264B1
公开(公告)日：2006-11-14
申请号：KR1020050105534
申请日：2005-11-04
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/02
Abstract: A method for growing a III-V group compound semiconductor quantum dot through interception of a periodic supply of a V-group element is provided to properly control mobility of a III-group element on the surface of a substrate by continuously supplying a III-group element when a quantum dot is grown on the substrate wherein a supply of a V-group element is periodically intercepted. A buffer layer is grown on a semiconductor substrate in a chamber. A III-group element and a V-group element are supplied to grow a compound semiconductor quantum dot on the buffer layer wherein the III-group element is continuously supplied and the supply and interception of the V-group element are periodically repeated. The supply of the III-group element and the V-group element is intercepted.
Abstract translation: 通过截断V族元素的周期性供应来提供生长III-V族化合物半导体量子点的方法，以通过连续供应III族来适当地控制III族元素在衬底表面上的迁移率 当在衬底上生长量子点时，周期性截取V族元素的供应。 在腔室中的半导体衬底上生长缓冲层。 提供III族元素和V族元素以在连续提供III族元素的缓冲层上生长化合物半导体量子点，并周期性地重复供给和截取V族元素。 拦截III族元素和V族元素的供应。
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公开(公告)号：KR100540874B1
公开(公告)日：2006-01-11
申请号：KR1020030028168
申请日：2003-05-02
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/20
Abstract: 본 발명은 반도체 양자점(quantum dot) 구조 형성 방법에 관한 것으로서, 양자점의 발광 파장을 조절하는 동시에 양자점의 균일도를 증가시키는 것을 목적으로 한다. 본 발명에서는 반도체 기판 상에 양자점 층을 형성한 다음, 덮개층(capping layer)을 형성하기 전에, 격자 상수가 덮개층보다 작고 에너지 간격(band gap)은 덮개층보다 큰 이종 덮개층을 삽입한다. 이 이종 덮개층의 두께를 변화시키면 양자점의 발광 파장을 조절할 수 있고, 양자점을 더욱 균일하게 변형시켜 발광 파장의 반가폭을 줄일 수 있다. 따라서, 본 발명에 따른 양자점 구조를 양자점 레이저, 증폭기, 광 스위칭 등의 광소자로 응용할 때 그 소자 특성이 개선될 수 있다.
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公开(公告)号：KR100430813B1
公开(公告)日：2004-05-10
申请号：KR1020010049937
申请日：2001-08-20
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/20
Abstract: PURPOSE: A two-step growth interruption process for control of semiconductor quantum dot is provided to control a solid shape of a quantum dot by performing two growth interruption processes. CONSTITUTION: A chemical compound semiconductor buffer layer(110) is grown on a semiconductor substrate(100). A quantum dot crystallization layer is formed on the chemical compound semiconductor buffer layer(110). The grating constant of quantum dot crystallization layer is larger than that of the chemical compound semiconductor buffer layer(110). A quantum dot(320) of a solid shape is formed on the quantum dot crystallization layer by performing the first growth interruption process. The solid shape of the quantum dot(320) is controlled by performing the second growth interruption process. A cover layer(330) is grown on the quantum dot(320). The grating constant of the cover layer(330) is smaller than that of the quantum dot crystallization layer.
Abstract translation: 目的：通过执行两个生长中断过程来提供用于控制半导体量子点的两步生长中断过程以控制量子点的固体形状。 构成：化学化合物半导体缓冲层（110）生长在半导体衬底（100）上。 量子点结晶层形成在化合物半导体缓冲层（110）上。 量子点结晶层的光栅常数大于化合物半导体缓冲层（110）的光栅常数。 通过执行第一生长中断过程在量子点结晶层上形成固体形状的量子点（320）。 通过执行第二生长中断过程来控制量子点（320）的固体形状。 在量子点（320）上生长覆盖层（330）。 覆盖层（330）的光栅常数小于量子点结晶层的光栅常数。
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公开(公告)号：KR1020030087835A
公开(公告)日：2003-11-15
申请号：KR1020020025914
申请日：2002-05-10
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L27/108
Abstract: PURPOSE: A DRAM(Dynamic Random Access Memory) using a self aligned SOI(Silicon-On-Insulator) double gate transistor and a method for manufacturing the same are provided to be capable of solving the problems such as DIBL(Drain Induced Barrier Lowering) phenomenon, the increase of channel resistance, the increase of gate resistance, and junction leakage current. CONSTITUTION: After forming a double gate at the upper portion of a substrate, a cell is formed by forming a source/drain for CMOS(Complementary Metal Oxide Semiconductor) at the peripheral region of the double gate. Then, a direct contact and a buried contact(161) of the cell, are formed at the resultant structure. A metal contact is formed on the direct and buried contact.
Abstract translation: 目的：提供使用自对准SOI（绝缘体上硅）双栅极晶体管的DRAM（动态随机存取存储器）及其制造方法，以能够解决诸如DIBL（漏极诱导屏障降低） 现象，通道电阻的增加，栅极电阻的增加和结漏电流。 构成：在衬底的上部形成双栅极之后，通过在双栅极的外围区域形成用于CMOS（互补金属氧化物半导体）的源极/漏极来形成电池。 然后，在所得结构处形成电池的直接接触和埋入触点（161）。 在直接和埋置的触点上形成金属接触。
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Patent Agency Ranking
公开(公告)号：KR100948193B1
公开(公告)日：2010-03-16
申请号：KR1020080002327
申请日：2008-01-08
Applicant: 재단법인서울대학교산학협력재단
Abstract: 본 발명의 목적은 공정이 간단하고, 에너지 소모량이 감소되며, 넓은 영역 및 특정 모양의 영역에서 나노와이어의 성장이 가능하고, 나노와이어의 길이, 직경, 나노와이어의 분포 밀도, 나노와이어의 성장 속도 등의 조절이 가능한 인듐 나노와이어의 성장 방법을 제공하는 것이다. 이를 위하여 본 발명에서는, InGaN 기판을 준비하는 단계(a); 및 고진공 조건 하에서 상기 InGaN 기판 상의 소정의 위치에 집속 이온빔을 소정 시간 조사하여 상기 InGaN 기판 상의 집속 이온빔이 조사된 위치에서 인듐 나노와이어를 성장시키는 단계(b)를 포함하는 인듐 나노와이어의 제조 방법을 제공한다.
인듐 나노 와이어, GaN, InGaN, 이온빔-
公开(公告)号：KR1020090041858A
公开(公告)日：2009-04-29
申请号：KR1020070107577
申请日：2007-10-25
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/027 , H01L33/00 , A00
Abstract: A manufacturing method of a substrate on which a pattern is formed is provided to prevent damage generated in a dry etching by patterning oxide beads on a substrate with a desired shape. A manufacturing method of a substrate on which a pattern is formed comprises the following steps: a step for forming a first binding pattern having a selective binding force on a forming position of an oxide bead pattern of a substrate(S210); a step for coating a second binding to the oxide bead(S220); a step for forming the oxide bead on which the second binding is coated through a coating on the first binding pattern(S230); and a step for heat-treating the substrate(S240).
Abstract translation: 提供其上形成有图案的基板的制造方法，以防止在具有所需形状的基板上图案化氧化物珠粒的干蚀刻中产生的损伤。 其上形成图案的基板的制造方法包括以下步骤：在基板的氧化物珠图案的成形位置上形成具有选择性结合力的第一装订图案的步骤（S210）; 涂覆第二次结合氧化物珠的步骤（S220）; 用于形成通过第一结合图案上的涂层涂覆第二粘合物的氧化物珠粒的步骤（S230）; 和用于对基材进行热处理的步骤（S240）。
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公开(公告)号：KR1020080065557A
公开(公告)日：2008-07-14
申请号：KR1020080002327
申请日：2008-01-08
Applicant: 재단법인서울대학교산학협력재단
CPC classification number: C01G15/00 , B82Y30/00 , B82Y40/00 , C01P2004/16
Abstract: A method for growing indium nanowires is provided to have a simple process, to reduce energy consumption, and to control the length, diameter, distribution density and growth rate of nanowires. A method for growing indium nanowires includes the steps of: (a) providing an InGaN substrate(10); and (b) irradiating a predetermined position(10b) on the InGaN substrate with a focused ion beam(20) under a high vacuum condition for a predetermined time to grow indium nanowires at the position on the InGaN substrate irradiated with the focused ion beam. When the focused ion beam is applied, the growth condition of nanowires has a pressure range from 3.75x10^(-5) Pa to 2.75x10^(-3) Pa, a voltage range from 5.0 kV to 30 kV, and a current range from 3 pA to 1 nA.
Abstract translation: 提供了用于生长铟纳米线的方法，其具有简单的过程，以减少能量消耗，并且控制纳米线的长度，直径，分布密度和生长速率。 一种用于生长铟纳米线的方法包括以下步骤：（a）提供InGaN衬底（10）; 和（b）在高真空条件下用聚焦离子束（20）将InGaN衬底上的预定位置（10b）照射预定时间，以在被聚焦离子束照射的InGaN衬底上的位置上生长铟纳米线。 当聚焦离子束被施加时，纳米线的生长条件的压力范围为3.75×10 ^（-5）Pa至2.75×10 -3（-3）Pa，电压范围为5.0kV至30kV，电流范围 从3 pA到1 nA。
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公开(公告)号：KR1020070104091A
公开(公告)日：2007-10-25
申请号：KR1020060036248
申请日：2006-04-21
Applicant: 재단법인서울대학교산학협력재단
Abstract: A method for forming III-nitride semiconductor layer and an apparatus using the same are provided to use single crystal SiO2 substrate instead of a conventional sapphire substrate and a silicon carbide substrate. A method for forming III-nitride semiconductor layer includes the steps of: a first step of forming a buffer layer(32) on a single crystal SiO2 substrate(31); and a second step of forming the III-nitride semiconductor layer(33) on the buffer layer. In at least one between the first and second steps, the single crystal SiO2 substrate serves a displacive phase transition. The single crystal SiO2 substrate is any one selected from a group consisting of an alpha quartz, a beta quartz, a low tridymite, a high tridymite, a low cristobalite, a high cristobalite or the like.
Abstract translation: 提供了用于形成III族氮化物半导体层的方法及其使用方法，以使用单晶SiO 2衬底代替常规蓝宝石衬底和碳化硅衬底。 一种形成III族氮化物半导体层的方法包括以下步骤：在单晶SiO 2衬底（31）上形成缓冲层（32）的第一步骤; 以及在缓冲层上形成III族氮化物半导体层（33）的第二步骤。 在第一和第二步骤中的至少一个中，单晶SiO 2衬底用于置换相变。 单晶SiO 2衬底是从由α石英，β石英，低鳞石英，高鳞石英，低方英石，高方英石等组成的组中选择的任意一种。
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公开(公告)号：KR100590444B1
公开(公告)日：2006-06-19
申请号：KR1020030068329
申请日：2003-10-01
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/20
Abstract: 본 발명은 결함 밀도가 낮은 고품질 질화물 반도체 에피층 성장 방법에 관한 것이다. 본 발명에 따른 질화물 반도체 에피층 성장 방법에서는, 고온에서 얇은 두께의 평탄한 2차원 질화물 반도체 완충층을 성장시킨 후 온도를 낮추어 적정 성장 온도에서 상기 질화물 반도체 완충층과 동종의 질화물 반도체 에피층을 성장시킨다. 이러한 방법으로 성장시킨 질화물 반도체 에피층은 결함 밀도가 낮고 결정성이 양호하여 고효율 광소자 및 전자소자 제작에 유리하다.
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