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公开(公告)号：KR100440253B1
公开(公告)日：2004-07-15
申请号：KR1020020030540
申请日：2002-05-31
Applicant: 한국전자통신연구원
IPC: H01L29/737
Abstract: PURPOSE: An optical receiver is provided to improve reception sensitivity and an amplification characteristic by integrating a waveguide-type optical detector and a n+InP/p+InGaAs/n-InGaAs/n+InGaAs heterojunction bipolar transistor(HBT) on a half-insulated substrate wherein a pn junction is formed in the waveguide-type optical detector and the HBT amplifies an electrical signal converted by the optical detector. CONSTITUTION: A p+InGaAs layer(202), a p+InAlAs layer(203), an n+InAlAs layer(204) and an n+InGaAs sub-collector layer(205) are stacked in a predetermined region on the half-insulated InP substrate(201). An n-InGaAs layer and a p+InGaAs base layer are stacked in a predetermined region on the n+InGaAs sub-collector layer to transfer high speed current. An n+InP emitter layer and an n+InGaAs ohmic layer are stacked in a predetermined region on the p+InGaAs base layer. An emitter electrode(212) is formed on the n+InGaAs ohmic layer. A base electrode(213) is formed in a predetermined region on the p+InGaAs base layer. A collector electrode(214) is formed in a predetermined region on the n+InGaAs sub-collector layer.
Abstract translation: 目的：提供一种光接收器，用于通过在半波片上集成波导型光检测器和n + InP / p + InGaAs / n-InGaAs / n + InGaAs异质结双极晶体管（HBT）来提高接收灵敏度和放大特性。 其中在波导型光学检测器中形成pn结，并且HBT放大由光学检测器转换的电信号。 构成：在半导体基板的规定区域层叠p + InGaAs层（202），p + InAlAs层（203），n + InAlAs层（204）和n + InGaAs子集电极层（205） 绝缘的InP衬底（201）。 在n + InGaAs子集电极层上的预定区域中堆叠n-InGaAs层和p + InGaAs基极层以传输高速电流。 n + InP发射极层和n + InGaAs欧姆层堆叠在p + InGaAs基极层上的预定区域中。 发射电极（212）形成在n + InGaAs欧姆层上。 基极（213）形成在p + InGaAs基极层上的预定区域中。 集电极（214）形成在n + InGaAs子集电极层上的预定区域中。
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公开(公告)号：KR100438895B1
公开(公告)日：2004-07-02
申请号：KR1020010086533
申请日：2001-12-28
Applicant: 한국전자통신연구원
IPC: H01L27/04
CPC classification number: H01L29/7785
Abstract: A pseudomorphic high electron mobility transistor (PHEMT) power device formed on a double planar doped epitaxial substrate and capable of operating with a single voltage source and a method for manufacturing the PHEMT power device are provided. The PHEMT power device includes: an epitaxial substrate including a GaAs buffer layer, an AlGaAs/GaAs superlattice layer, an updoped AlGaAs layer, a first doped silicon layer, a first spacer, an InGaAs electron transit layer, a second spacer, a second doped silicon layer having a different doping concentration from the first doped silicon layer, a lightly doped AlGaAs layer, and an undoped GaAs cap layer stacked sequentially on a semi-insulating GaAs substrate, a source electrode and a drain electrode formed on and in ohmic contact with the undoped GaAs cap layer; and a gate electrode formed on the lightly doped AlGaAs layer to extend through the undoped GaAs cap layer.
Abstract translation: 提供一种形成在双平面掺杂外延衬底上并且能够利用单个电压源来操作的伪晶高电子迁移率晶体管（PHEMT）功率器件以及用于制造PHEMT功率器件的方法。 该PHEMT功率器件包括：外延衬底，包括GaAs缓冲层，AlGaAs / GaAs超晶格层，上掺杂AlGaAs层，第一掺杂硅层，第一间隔物，InGaAs电子传输层，第二间隔物，第二掺杂 硅层，其具有与第一掺杂硅层不同的掺杂浓度，轻掺杂AlGaAs层和未掺杂GaAs帽层，其依次堆叠在半绝缘GaAs衬底上，源电极和漏电极形成在第一掺杂硅层上并与其欧姆接触 未掺杂的GaAs帽盖层; 以及形成在轻掺杂AlGaAs层上以延伸穿过未掺杂的GaAs帽层的栅电极。
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公开(公告)号：KR1020020080906A
公开(公告)日：2002-10-26
申请号：KR1020010020763
申请日：2001-04-18
Applicant: 한국전자통신연구원
Inventor： 김해천
IPC: H01L21/20
Abstract: PURPOSE: A method for fabricating a gallium arsenide active layer is provided to maintain a uniform characteristic of a device, by preventing silicon atoms in a silicon nitride layer from being diffused to the inside of gallium arsenide in a high temperature heat treatment process. CONSTITUTION: Silicon is doped to a portion under the surface of a gallium arsenide substrate(1). Oxygen is implanted to perform a plasma treatment process. A passivation layer(3) for preventing evaporation of arsenide is formed on the front surface or both surfaces of the plasma-treated substrate. A rapid thermal process is performed on the resultant structure.
Abstract translation: 目的：提供一种制造砷化镓活性层的方法，以通过防止氮化硅层中的硅原子在高温热处理工艺中扩散到砷化镓内部来保持器件的均匀特性。 构成：将硅掺杂到砷化镓衬底（1）的表面下方的部分。 植入氧气以进行等离子体处理过程。 在等离子体处理的基板的前表面或两个表面上形成用于防止砷化物蒸发的钝化层（3）。 对所得结构进行快速热处理。
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公开(公告)号：KR1020010053771A
公开(公告)日：2001-07-02
申请号：KR1019990054279
申请日：1999-12-01
Applicant: 한국전자통신연구원
IPC: H01L21/306
Abstract: PURPOSE: A method for photoelectrochemical etching of a semiconductor using an energy band bending is provided to improve an etching speed for the third group-nitrides by using a diluted etching solution. CONSTITUTION: An etching mask(3) is formed on a predetermined portion of a substrate(1). A resistance contact portion(4) is formed at one part of the substrate(1). An electric power is applied to the resistant contact portion(4). An insulating layer(6) is formed in order not to expose a connection portion between the resistance contact portion(4) and the power. The substrate(1) and the other electrode connected with the power source are soaked into an etching solution(11). A well is formed on a surface of the substrate(1) by applying the power to the substrate(1). An etching process is performed by irradiating the light larger than an energy gap of the substrate(1).
Abstract translation: 目的：提供使用能带弯曲对半导体进行光电化学蚀刻的方法，以通过使用稀释蚀刻溶液来提高第三组氮化物的蚀刻速度。 构成：在基板（1）的预定部分上形成蚀刻掩模（3）。 电阻接触部分（4）形成在衬底（1）的一部分处。 电力施加到电阻接触部分（4）上。 为了不暴露电阻接触部分（4）和电源之间的连接部分，形成绝缘层（6）。 将衬底（1）和与电源连接的另一电极浸入蚀刻溶液（11）中。 通过向基板（1）施加电力，在基板（1）的表面上形成阱。 通过照射比基板（1）的能隙大的光来进行蚀刻处理。
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公开(公告)号：KR100223021B1
公开(公告)日：1999-10-01
申请号：KR1019960033694
申请日：1996-08-14
Applicant: 한국전자통신연구원
IPC: H01L21/28
Abstract: 본 발명은 T형 게이트 제조 방법에 관한 것으로, 스탭퍼를 사용하여 실리콘 나이트라이드의 증착 및 건식 식각에 의하여 게이트길이가 짧은 T-형 게이트를 제조하므로서, 게이트 길이가 짧게 형성되면서도 게이트 저항이 증가하지 않아 소자의 이득 및 잡음 특성이 나빠지지 않고, 일반 스탭퍼의 패턴 해결(Resolution)의 한계인 0.5 보다 훨씬 작은 0.1-0.2
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Patent Agency Ranking
公开(公告)号：KR100138873B1
公开(公告)日：1998-06-01
申请号：KR1019940036333
申请日：1994-12-23
Applicant: 한국전자통신연구원
IPC: H01L21/334
Abstract: 본 발명은 갈륨비소 화합물 반도체의 활성층을 형성할 수 있는 기존의 고가 장비를 사용하지 않고, 유황을 화학용액에 담그는 간단한 처리방법에 의해 소자의 활성층을 제조함으로써, 소자의 제작공정 시간을 줄일 수 있고, 소자 제작 단가를 낮출 수 있다는 장점을 갖고 있다.
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公开(公告)号：KR1019970002438B1
公开(公告)日：1997-03-05
申请号：KR1019930029633
申请日：1993-12-24
Applicant: 한국전자통신연구원
IPC: H01L21/3205
Abstract: A thin film conductive layer structure for gold plating for the purpose of forming an airbridge is provided, which is constructed in such a manner that a metal pad layer 1 is formed using a first resist layer 2, a thin film conductive layer 3 is formed on the overall surface of a wafer, a second resist layer 4 is coated on a predetermined portion of the first resist layer 2, a gold-plating layer 5 is formed on a predetermined portion where the second resist layer 4 is not coated, and the resist layers 2 and 4 and thin film conductive layer 3 are removed. The thin film conductive layer 3 is configured of a three-level structure and includes an adhesion layer 6, made of Cr or Ti, for increasing the adhesive strength between the gold-plating layer 5 and first resist layer 2, a conductive layer 7, made of Ni, having a predetermined thickness of above 100 angstrom, to be used in plating, and a surface protection layer 8, made of Au with a thickness of below 50 angstrom, for preventing the native oxide layer being formed on thethin film conductive layer.
Abstract translation: 提供了一种用于形成空气桥的用于镀金的薄膜导电层结构，其以使用第一抗蚀剂层2形成金属焊盘层1的方式构造，在 晶片的整个表面，第二抗蚀剂层4涂覆在第一抗蚀剂层2的预定部分上，在未涂覆第二抗蚀剂层4的预定部分上形成镀金层5，并且抗蚀剂 层2和4以及薄膜导电层3被去除。 薄膜导电层3由三层结构构成，并且包括由Cr或Ti制成的用于增加镀金层5和第一抗蚀剂层2之间的粘合强度的粘合层6，导电层7， 由具有预定厚度的100埃以上的Ni制成，用于电镀，以及由Au制成的厚度低于50埃的表面保护层8，用于防止在该导电层上形成的天然氧化物层 。
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公开(公告)号：KR1019960039223A
公开(公告)日：1996-11-21
申请号：KR1019950009258
申请日：1995-04-19
Applicant: 한국전자통신연구원
IPC: H01L21/338 , H01L29/812
Abstract: 본 발명은 금속-반도체 전계효과 트랜지스터(MESFET:metalsemiconductor field effect transistor), 고전자 이동도 트랜지스터(HEMT : high electron mobility transistor) 또는 이종접합 바이폴라 트랜지스터(HBT : heter-ojuntion bipolar transistor) 등과 같은 갈륨비소 화합물 반도체 소자의 제조방법에 관한 것으로, 특히 상기 소자의 게이트 전극 형성방법에 관한 것이다.
본 발명은 게이트 전극으로 사용되는 금속층을 형성하는 공정전에 웨이퍼의 표면을 황화암모늄[(NH
4 )
2 S
x ] 용액으로 유황처리하는 공정을 포함함을 특징으로 하며, 상기 유황처리 공정에 의해 웨이퍼의 표면상태밀도가 낮아지고, 이에 따른 쇼트키 장벽높이가 의도하는 만큼 얻어질 수 있다.-
公开(公告)号：KR1019960026482A
公开(公告)日：1996-07-22
申请号：KR1019940035464
申请日：1994-12-21
Applicant: 한국전자통신연구원
IPC: H01L21/304
Abstract: 본 발명은 오옴익층의 새로운 금속구조를 제시한다.
오옴익층의 형성과정은 종래의 방법과 동일하나 금속구조가 기판으로부터 Ni/Ge/Au/Ti/Au의 적층을 이룬다.
이를 약 400℃정도의 온도에서 20초 정도 열처리를 수행하여 오옴익층을 형성한다.
본 발명에 의한 오옴익층은 종래의 구조에 비하여 접촉저항값이 향상될 뿐아니라, 표면 조직과 열안정성 역시 향상되는장점을 가진다.-
公开(公告)号：KR102261740B1
公开(公告)日：2021-06-09
申请号：KR1020170027956
申请日：2017-03-03
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/02 , H01L21/027 , H01L29/66 , H01L29/423 , H01L29/45 , H01L21/762
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