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公开(公告)号：KR1020040055085A
公开(公告)日：2004-06-26
申请号：KR1020020081680
申请日：2002-12-20
Applicant: 한국전자통신연구원
IPC: H03L7/097
Abstract: PURPOSE: A frequency synthesizer for multi-band and a method for synthesizing a frequency are provided to process the multi-band under the low power by using a VCO(Voltage Controlled Oscillator). CONSTITUTION: A frequency/phase detector(200) compares a reference frequency with a feedback frequency and outputs a compared result. A charge pump circuit(300) converts the compared result to the current. A low pass filter(400) generates a voltage corresponding to the output current of the charge pump circuit. A VCO(500) outputs a voltage controlled frequency corresponding to an output voltage of the low pass filter. A division circuit(600) divides the voltage controlled frequency of the VCO by a band selection ratio and outputs a desired band frequency. A channel selection division circuit(700) divides the band frequency by a channel selection ratio and generates the feedback frequency.
Abstract translation: 目的：提供用于多频带的频率合成器和用于合成频率的方法，以通过使用VCO（压控振荡器）在低功率下处理多频带。 构成：频率/相位检测器（200）将参考频率与反馈频率进行比较，并输出比较结果。 电荷泵电路（300）将比较结果转换成电流。 低通滤波器（400）产生对应于电荷泵电路的输出电流的电压。 VCO（500）输出对应于低通滤波器的输出电压的电压控制频率。 分频电路（600）将VCO的压控频率除以频带选择比，并输出期望的频带频率。 频道选择分频电路（700）将频带频率除以频道选择比，并产生反馈频率。
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公开(公告)号：KR1020040055084A
公开(公告)日：2004-06-26
申请号：KR1020020081679
申请日：2002-12-20
Applicant: 한국전자통신연구원
IPC: H03L7/08
Abstract: PURPOSE: A frequency synthesizer for detecting current of a charge pump circuit is provided to minimize a delay time of a delay signal for resetting a frequency/phase detector by predicting accurately the variation according to various conditions. CONSTITUTION: A frequency synthesizer for detecting current of a charge pump circuit includes a frequency/phase detector, a charge pump circuit, and a current detector. The frequency/phase detector(100) is used for receiving the first frequency and outputting the first and the second control signals corresponding the first frequency. The charge pump circuit(200) is used for outputting the first current and the second current in response to the first and the second control signals. The current detector(300) is used for detecting a period when the first current and second current flow simultaneously, and outputting a delay signal for resetting the frequency/phase detector.
Abstract translation: 目的：提供一种用于检测电荷泵电路电流的频率合成器，用于通过根据各种条件准确地预测变化来最小化用于复位频率/相位检测器的延迟信号的延迟时间。 构成：用于检测电荷泵电路的电流的频率合成器包括频率/相位检测器，电荷泵电路和电流检测器。 频率/相位检测器（100）用于接收第一频率并输出对应于第一频率的第一和第二控制信号。 电荷泵电路（200）用于响应于第一和第二控制信号输出第一电流和第二电流。 电流检测器（300）用于同时检测第一电流和第二电流的周期，并且输出用于复位频率/相位检测器的延迟信号。
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公开(公告)号：KR1020030047565A
公开(公告)日：2003-06-18
申请号：KR1020010078268
申请日：2001-12-11
Applicant: 한국전자통신연구원
IPC: H03L7/00
CPC classification number: H03M7/3022 , H03L7/1978
Abstract: PURPOSE: A structure of a delta sigma divider is provided to obtain the capacity to synthesize the broadband frequency and maximize an effect of a delta sigma method by adding an output value of a delta sigma modulator to an external input value to modulate a value of a swallow counter. CONSTITUTION: A delta sigma modulator(41) is used for receiving a frequency and an external input value. A swallow adder block(40) is used for adding an external input value to an output value of the delta sigma modulator. A program register block(37) is used for storing an output value of the swallow adder block. A pulse swallow counter block(34) is formed with a dual modulus prescaler, a program counter, and a swallow counter in order to divide an input frequency according to a stored value of the program register block.
Abstract translation: 目的：提供Δ-Σ分配器的结构，以获得合成宽带频率的能力，并通过将Δ-Σ调制器的输出值与外部输入值相加来调整Δ值 吞咽计数器 构成：ΔΣ调制器（41）用于接收频率和外部输入值。 吞咽加法器块（40）用于将外部输入值添加到delta-Σ调制器的输出值。 程序寄存器块（37）用于存储吞咽加法器块的输出值。 脉冲吞咽计数器块（34）由双模预分频器，程序计数器和吞咽计数器形成，以便根据程序寄存器块的存储值对输入频率进行分频。
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公开(公告)号：KR100345397B1
公开(公告)日：2002-07-26
申请号：KR1019990062446
申请日：1999-12-27
Applicant: 한국전자통신연구원
IPC: H03L7/00
Abstract: 본발명은기준신호와비교신호를비교하여위상차신호를생성하는위상비교기와, 위상비교기로부터의위상차신호에기초한펄스성분을포함하는 DC 성분을갖는전압신호를생성하는차지펌프와, 차지펌프로부터공급된전압신호를평활화하여고주파성분이제거된제어전압을생성하는로우패스필터와, 주파수가제어전압의값에대응하는출력신호를출력하는전압제어발진기와, 전압제어발진기로부터생성된출력신호는피드백하는분주회로를구비하는주파수합성기에있어서, 분주회로는복수의상단 T 플립플롭과, 복수의하단 D 플립플롭을구비함으로써, 분주회로에의한지연시간을단축시키는주파수합성기를제공한다.
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公开(公告)号：KR1020010063876A
公开(公告)日：2001-07-09
申请号：KR1019990061980
申请日：1999-12-24
Applicant: 한국전자통신연구원
IPC: H03B28/00
Abstract: PURPOSE: A low noise current controlled oscillator having wide band variation characteristic is provided to enable a wide band variation at a low voltage on maintaining a low noise characteristic that an L-C oscillator has the same characteristic by improving the oscillator structure. CONSTITUTION: The first through fourth inductors(L1 to L4) are coupled to a power source(VDD), respectively. The first and second transconductors(M1,M2) are coupled to the first and second inductors(L1,L2), respectively, while the third and fourth transconductors(M3,M4) are coupled to the third and fourth inductors(L3,L4), respectively. The fifth and sixth transconductors(M5,M6) are coupled to the third and fourth inductors(L3,L4) and the first and second transconductors(M1,M2), respectively. The seventh and eighth transconductors(M7,M8) are coupled to the first and second inductors(L1,L2) and the third and fourth transconductors(M3,M4). A main current source adjustment element(VB1) is coupled with between a node of the fifth and sixth transconductors(M5,M6) and a ground and between a node of the seventh and eighth transconductors(M7,M8) and the ground. A subsidiary current source adjustment element(VB2) is coupled with between a node of the first and second transconductors(M1,M2) and the ground and between a node of the third and fourth transconductors(M3,M4) and the ground.
Abstract translation: 目的：提供具有宽带变化特性的低噪声电流控制振荡器，以便通过改善振荡器结构来保持L-C振荡器具有相同特性的低电压宽带变化。 构成：第一至第四电感器（L1至L4）分别耦合到电源（VDD）。 第一和第二跨导体（M1，M2）分别耦合到第一和第二电感器（L1，L2），而第三和第四跨导体（M3，M4）耦合到第三和第四电感器（L3，L4） ， 分别。 第五和第六跨导体（M5，M6）分别耦合到第三和第四电感器（L3，L4）和第一和第二跨导体（M1，M2）。 第七和第八跨导体（M7，M8）耦合到第一和第二电感器（L1，L2）以及第三和第四跨导体（M3，M4）。 主电流源调节元件（VB1）与第五和第六跨导体（M5，M6）的节点和地之间以及第七和第八跨导体（M7，M8）的节点和地之间耦合。 辅助电流源调节元件（VB2）与第一和第二跨导体（M1，M2）的节点和地之间以及第三和第四跨导体（M3，M4）的节点与地之间耦合。
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Patent Agency Ranking
公开(公告)号：KR1020160100100A
公开(公告)日：2016-08-23
申请号：KR1020150022651
申请日：2015-02-13
Applicant: 한국전자통신연구원
CPC classification number: H03F1/3241 , H03F1/3211 , H03F3/193 , H03F3/45179 , H03F3/45475 , H03F2200/451 , H03G5/28 , H03H11/0466 , H03H11/0472 , H03H7/12 , H03H7/002 , H03H7/03 , H03H2210/017
Abstract: 넓은범위의이득조절을제공하는대역통과필터가제공된다. 대역통과필터는채널필터링및 이득조절을수행하면서도, 대역통과필터의대역통과특성을유지한다. 대역통과필터는넓은신호크기범위에대한이득제어를가능하게하면서도, 높은선형성을가질수 있는통과대역외 감쇠비 특성및 통과대역내 낮은평탄도등의성능을일정하게얻을수 있다.
Abstract translation: 提供了一种提供宽增益控制范围的带通滤波器。 带通滤波器在保持带通滤波器的带通特性的同时进行信道滤波和增益控制。 带通滤波器能够在宽的信号幅度范围内控制增益，并且稳定地获得诸如带外衰减比和低带内平坦度等性能特性，具有高线性度。
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公开(公告)号：KR101354650B1
公开(公告)日：2014-01-21
申请号：KR1020100035946
申请日：2010-04-19
Applicant: 한국전자통신연구원
IPC: H03M1/38
Abstract: 본 발명은 최소한의 캐패시터만을 구비하여 아날로그-디지털 변환 동작을 수행될 수 있도록 함으로써, 감소된 정전 용량과 회로 면적을 가질 수 있을 뿐 만 아니라 공정 변화에도 매우 강한 특성을 가질 수 있도록 하는 연속 근사 아날로그-디지털 데이터 변환기에 관한 것으로, 상기 연속 근사 아날로그-디지털 데이터 변환기는 기준전류를 공급하는 기준전류 공급부; 상기 기준전류를 충전하여 생성되는 기준신호와 외부로부터 입력되는 입력신호를 저장하는 신호 저장부; 상기 기준신호와 상기 입력신호를 비교하는 비교부; 상기 비교부의 비교 결과를 기반으로 디지털 출력신호를 발생함과 동시에 상기 기준전류 공급부를 제어하여 상기 신호 저장부에 공급되는 기준전류의 공급량이 이진코드에 비례하여 변화되도록 하는 제어부를 포함할 수 있다.
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公开(公告)号：KR1020130036697A
公开(公告)日：2013-04-12
申请号：KR1020120052201
申请日：2012-05-16
Applicant: 한국전자통신연구원
IPC: H04L27/18
CPC classification number: H04L27/20
Abstract: PURPOSE: A device for inputting the signal of a digital-RF converter is provided to improve a signal-noise ratio by generating noise generated by the excessive response of an input signal in a specific frequency or a random frequency. CONSTITUTION: A device for inputting the signal of a digital-RF converter(100) includes a phase-modulated signal input unit inputting a phase-modulated transmission signal into the LO switch(130) of the digital-RF converter; and a digital signal input unit modifying a digital signal in order to correspond to the phase-modulated transmission signal and inputting the modified digital signal into the data switch(121,122) of the digital-RF converter.
Abstract translation: 目的：提供用于输入数字RF转换器的信号的装置，用于通过产生由特定频率或随机频率的输入信号的过度响应产生的噪声来提高信噪比。 构成：用于输入数字RF转换器（100）的信号的装置包括相位调制信号输入单元，其将相位调制的发送信号输入到数字RF转换器的LO开关（130）中; 以及数字信号输入单元，其修改数字信号以便对应于相位调制的传输信号，并将修改的数字信号输入到数字RF转换器的数据开关（121,122）中。
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公开(公告)号：KR1020130029346A
公开(公告)日：2013-03-22
申请号：KR1020120101370
申请日：2012-09-13
Applicant: 한국전자통신연구원
IPC: H03D7/00
Abstract: PURPOSE: A programmable demodulation frequency mixer is provided to improve the performance of a transceiver by reducing a process band width of the transceiver, power consumption, and the size of a chip. CONSTITUTION: A programmable demodulation frequency mixer(20) includes an I/Q signal changing unit(210), a mixer unit(220), and a calculating unit(230). The mixer unit changes an I signal and a Q signal inputted from an I/Q signal input unit according to an oscillation signal generated from an oscillator. The calculating unit adds up or deducts the I and Q signals inputted the mixer unit in order to generate an output signal. The I/Q signal changing unit adjusts a path and a symbol of the I and Q signals inputted from the calculating unit or the mixer unit according to an I/Q control signal. [Reference numerals] (10) I/Q signal input unit; (211) First I/Q signal changing part; (212) Second I/Q signal changing part; (231) First calculator; (232) Second calculator; (240) Oscillator; (250) Oscillation signal changing unit; (30) I/Q signal processing unit
Abstract translation: 目的：提供可编程解调混频器，通过降低收发器的工艺带宽，功耗和芯片尺寸来提高收发器的性能。 构成：可编程解调混频器（20）包括I / Q信号改变单元（210），混频器单元（220）和计算单元（230）。 混频器单元根据从振荡器产生的振荡信号改变从I / Q信号输入单元输入的I信号和Q信号。 计算单元相加或减去输入混频器单元的I和Q信号，以产生输出信号。 I / Q信号改变单元根据I / Q控制信号调整从计算单元或混频器单元输入的I和Q信号的路径和符号。 （附图标记）（10）I / Q信号输入单元; （211）第一I / Q信号变换部; （212）第二I / Q信号变换部分; （231）第一计算器; （232）第二计算器; （240）振荡器; （250）振荡信号改变单元; （30）I / Q信号处理单元
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公开(公告)号：KR1020120072217A
公开(公告)日：2012-07-03
申请号：KR1020100134051
申请日：2010-12-23
Applicant: 한국전자통신연구원
IPC: H01P1/36
Abstract: PURPOSE: A programmable active isolator for cancelation of a leakage is provided to improve the linearity of a whole system by eliminating a leakage of RF signals without using frequency conversion. CONSTITUTION: A main isolating unit(110) is arranged in a main route. A leakage removal unit(120) including a voltage reducer(121) and a phase shifter(122) is arranged in a branch route branched off the main route and removes leaked signals. In the leakage removal unit, the voltage reducer and the phase shifter are integrated into a single chip.
Abstract translation: 目的：提供用于消除泄漏的可编程有源隔离器，通过消除RF信号的泄漏而不使用频率转换来提高整个系统的线性度。 构成：主隔离单元（110）布置在主路线上。 在从主路径分支的分支路径中设置包括减压器（121）和移相器（122）的泄漏去除单元（120），并且去除泄漏的信号。 在泄漏去除单元中，降压器和移相器集成到单个芯片中。
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