公开(公告)号：DE60336237D1

公开(公告)日：2011-04-14

申请号：DE60336237

申请日：2003-06-03

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETH ANN ,  SADANA DEVENDRA K

IPC: H01L21/336 ,  H01L27/088 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786

公开(公告)号：DE60335981D1

公开(公告)日：2011-03-24

申请号：DE60335981

申请日：2003-03-19

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FRIED DAVID M ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/786

公开(公告)号：AT500610T

公开(公告)日：2011-03-15

申请号：AT03736783

申请日：2003-06-03

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD ,  RAINEY BETH ,  SADANA DEVENDRA

IPC: H01L21/336 ,  H01L27/088 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786

Abstract: The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while providing improved wafer to wafer device uniformity. Specifically, the method facilitates the formation of finFET devices from bulk semiconductor wafers with improved fin height control. Additionally, the method provides the ability to form finFETs from bulk semiconductor while providing isolation between fins and between the source and drain region of individual finFETs. Finally, the method can also provide for the optimization of fin width. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

公开(公告)号：DE10296953B4

公开(公告)日：2010-04-08

申请号：DE10296953

申请日：2002-06-06

Applicant: IBM

Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

IPC: H01L21/283 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

Abstract: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

公开(公告)号：DE602004015793D1

公开(公告)日：2008-09-25

申请号：DE602004015793

申请日：2004-06-30

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L29/06 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

公开(公告)号：AU2002317778A1

公开(公告)日：2003-01-08

申请号：AU2002317778

申请日：2002-06-06

Applicant: IBM

Inventor： BRYANT ANDRES ,  RANKIN JED ,  IEONG MEIKEI ,  MULLER K PAUL ,  FRIED DAVID M ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28

Abstract: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.