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    Generating monotonically increasing time of day values in multiprocessors
    22.
    发明专利
    Generating monotonically increasing time of day values in multiprocessors 未知

    公开(公告)号：GB2502540A

    公开(公告)日：2013-12-04

    申请号：GB201209548

    申请日：2012-05-30

    Applicant: IBM

    Inventor： LEHNERT FRANK ,  JACOBI CHRISTIAN ,  GERWIG GUENTER ,  SHUM CHUNG-LUNG K ,  SLEGEL TIMOTHY J

    IPC: G06F1/14

    Abstract: Method for generating monotonically increasing time-OF-day (TOD) values in a multiprocessor system, comprising: receiving synchronization impulses 532; and refusing an execution of read instruction of a time-of-day value (STCK B) within processor 504 of the system if said execution is requested after a predefined time after a synchronization impulse, and if trigger signal 502a, indicative of new data received by a related memory 202 external to the processor, has been received after the predefined time. The predefined time is the smallest latency for data value transfer between processors. The memory is a shared cache. The synchronisation pulses are received from PLL 530. A time flag is set after the predetermined time is reached while a reject flag is set if time flag is set and the trigger signal is received. TOD execution is rejected if reject flag is set. Said flags are reset upon reception of synchronisation impulses.

    Verfahren und System zur kontinuierlichen Bereitstellung eines Präzisionssystemakts
    24.
    发明专利
    Verfahren und System zur kontinuierlichen Bereitstellung eines Präzisionssystemakts 未知

    公开(公告)号：DE102012203531A1

    公开(公告)日：2012-09-27

    申请号：DE102012203531

    申请日：2012-03-06

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  VON BUTTLAR JOACHIM ,  LEHNERT FRANK ,  ENGLER EBERHARD ,  MEISSNER KLAUS

    IPC: G06F1/04

    Abstract: Die Erfindung betrifft ein Verfahren zur kontinuierlichen Bereitstellung eines Präzisionssystemtakts, der einem Prozessorkern (2) zugeordnet ist, wobei der Systemtakt ein Host-Taktregister (5) umfasst, das mithilfe eines Präzisionsoszillators aktualisiert wird, das Verfahren die Schritte des Bereitstellens eines Firmware-Taktregisters (6), des Hochzählens des Firmware-Taktregisters (6) bei jedem Hochzählen des Host-Taktregisters (5), der Überwachung von Ausfällen des Host-Taktregisters (5) und bei einem Ausfall des Host-Taktregisters (5) das kontinuierliche Hochzählen des Firmware-Taktregisters (6) mithilfe von Zeitsignalen des Prozessorkerns (2) sowie bei Empfang einer Anforderung auf Bereitstellung eines Taktwertes das Bereitstellen des Inhalts des Host-Taktregisters (5) umfasst, wenn kein Ausfall festgestellt wurde, und andernfalls den Inhalt des Firmware-Taktregisters (6).

    Updating corrupted local working registers in a multi-staged pipelined execution unit by refreshing from the last state hold a global checkpoint array
    26.
    发明专利
    Updating corrupted local working registers in a multi-staged pipelined execution unit by refreshing from the last state hold a global checkpoint array 未知

    公开(公告)号：GB2456891A

    公开(公告)日：2009-08-05

    申请号：GB0823186

    申请日：2008-12-19

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  MAYER ULRICH ,  LEHNERT FRANK ,  SHUM KEVIN CHUNG-LUNG

    IPC: G06F9/38 ,  G06F11/00

    Abstract: Disclosed is a method for updating corrupted local working registers in a multi-staged pipeline structure, after an exception. The registers being needed to execute complex instructions in an execution unit, e.g. a floating-point unit, whose deep pipeline structure comprises a set of local working registers. The pipeline being such data dependencies among different instructions referencing the same registers exist. The method operates by refreshing any corrupted local working register from the last architected state hold in a global checkpoint array. The registers may also be updated using the hardware infrastructure of the execution unit when the data is corrupted by early pipeline updates. A master copy of all local working registers may be held in the checkpoint array, which is not updated in exception cases. All the early loads or early register updates form instructions that were issued after an instruction got into the exception may be refreshed.

    Clock gating system for macro circuits on a semiconductor chip
    27.
    发明专利
    Clock gating system for macro circuits on a semiconductor chip 未知

    公开(公告)号：GB2456202A

    公开(公告)日：2009-07-08

    申请号：GB0821970

    申请日：2008-12-02

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  LEHNERT FRANK ,  MAYER ULRICH

    IPC: G06F1/10 ,  G06F1/32

    Abstract: A digital circuit on a semiconductor chip comprises a plurality of macro circuits (10, 12, 14) and a clock gating system (50, 52, 54) for disabling the clock signal for at least one single macro circuit (12) to reduce power consumption. The circuit comprises a hierarchical structure with at least two clock gating levels, and each macro circuit (10, 12, 14) is associated with one of the levels. A macro control circuit (10) is provided on a top clock gating level and controls the clock gating of at least one other macro circuit (12) on one or more lower clock gating levels, wherein all external signals used to control the clock gating are connected to the control circuit (10). The method distinguishes between two clock gating granularities. A coarse-grain gating operates on the boundaries of the macro circuits, and a fine-grain gating operates mainly on dataflow storage elements within the macro circuits.

    28.
    发明专利
    未知

    公开(公告)号：DE19614480C2

    公开(公告)日：2000-09-07

    申请号：DE19614480

    申请日：1996-04-12

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  DAO TRONG SON ,  GETZLAFF KLAUS ,  HALLER WILHELM

    IPC: G06F7/485 ,  G06F7/00 ,  G06F7/50 ,  G06F7/507 ,  G06F7/74

    Abstract: PCT No. PCT/EP95/01455 Sec. 371 Date May 13, 1997 Sec. 102(e) Date May 13, 1997 PCT Filed Apr. 18, 1995 PCT Pub. No. WO96/33456 PCT Pub. Date Oct. 24, 1996A method and apparatus for the determination of leading zero digits of a sum is presented herein. The technique incorporates the parallel determination of partial sums of single digits accounting for the possibility of carries and on the basis thereof the pre-determination of potential zero digits or potential leading zero digits. Upon the establishment of a correct partial sum, the potential zero digits are selected and evaluated thereby determining the leading zero digits. The invention may be implemented in an adder in parallel or via a hierarchical structure. The parallelism permits time-savings in the determination of a normalized sum. The invention is preferably incorporated into adders, floating point computing units and/or data processing units.

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