公开(公告)号：WO2007112432A3

公开(公告)日：2009-03-26

申请号：PCT/US2007065324

申请日：2007-03-28

Applicant: IBM ,  LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

Inventor： LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/2022 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

Abstract: Expitaxial substitutional solid solutions of silicon carbon (101 ) can be obtained by an ultra-fast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials (101 ) with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si1-yCy, y

Abstract translation: 可以通过非晶态含碳硅材料的超快速退火获得硅碳（101）的外延替代固溶体。 退火在高于再结晶点的温度下进行，但低于材料的熔点，并且在该温度范围内优选持续小于100毫秒。 退火优选是闪光退火或激光退火。 该方法能够产生具有替代晶格位置的大部分碳原子的外延硅和含碳材料（101）。 该方法在CMOS工艺和其他电子器件制造中特别有用，其中外延Si1-yCy，y <0.1对于应变工程或带隙工程是需要的。

公开(公告)号：WO2006065759A3

公开(公告)日：2007-06-14

申请号：PCT/US2005044957

申请日：2005-12-13

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

Abstract translation: 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠 所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：WO0198563A3

公开(公告)日：2002-05-30

申请号：PCT/US0119077

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： TEWS HELMUT HORST ,  FALTERMEIR JOHNATHAN E ,  MALIK RAJEEV ,  HEENAN CAROL ,  GLUSCHENKOV OLEG

IPC: C30B29/06 ,  C30B33/00 ,  H01L21/28 ,  H01L21/316 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L21/28185 ,  C30B29/06 ,  C30B33/00 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/76202 ,  H01L29/513 ,  H01L29/518 ,  Y10S438/973

Abstract: A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate (step 100) where surfaces have at least two different crystallographic orientations of the silicon crystal (step 102). Atomic oxygen (O) is formed for oxidizing the surfaces (step 106). An oxide is formed (step 108) on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.

Abstract translation: 根据本发明，在硅的至少两个结晶平面上形成基本均匀厚度的氧化物的方法包括提供其中表面具有硅晶体的至少两个不同晶体取向的衬底（步骤100）（步骤102 ）。 形成氧化表面的原子氧（O）（步骤106）。 通过使原子氧与表面反应，在表面上形成氧化物（步骤108），同时在表面上形成基本均匀的氧化物厚度。

公开(公告)号：WO2004066367A3

公开(公告)日：2009-05-28

申请号：PCT/US2004000968

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/76 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

Abstract: A low-GIRL current MOSFET device (90) structure and a method of fabrication thereof which provides a low-GIRL current. The MOSFET device structure contains a central gate conductor (10) whose edges may slightly overlap the source/drain diffusions (88, 88), and left and right side wing gate conductors (70,70) which are separated from the central gate conductor by a thin insulating and diffusion barrier layer (50, 52).

Abstract translation: 低GIRL电流MOSFET器件（90）结构及其制造方法，其提供低GIRL电流。 MOSFET器件结构包含中心栅极导体（10），其边缘可能与源极/漏极扩散（88,88）稍微重叠，并且左右翼栅极导体（70,70）与中心栅极导体分开， 薄的绝缘和扩散阻挡层（50,52）。

公开(公告)号：WO2008085686A2

公开(公告)日：2008-07-17

申请号：PCT/US2007088266

申请日：2007-12-20

Applicant: IBM ,  LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed suicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed suicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Abstract translation: 虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。 本发明提供了在放置在半导体衬底上的硅合金表面上提供非合金硅化物的结构和方法。 这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。 此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

公开(公告)号：WO0237561A2

公开(公告)日：2002-05-10

申请号：PCT/US0143859

申请日：2001-11-06

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： TEWS HELMUT ,  WEYBRIGHT MARY ,  KUDELKA STEPHAN ,  GLUSCHENKOV OLEG ,  HEGDE SURI

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/518 ,  Y10S438/981

Abstract: A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising:a) growing a sacrificial oxide layer on a substrate;b) implanting a dopant through the sacrificial oxide layer;c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface;e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide;f) implanting a second dosage of nitrogen ions through the photoresist;g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.

Abstract translation: 一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c） 不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以使氮气扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双重氧化物的薄氧化物的位置 栅极氧化物; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和h）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。

公开(公告)号：AU2021291163B2

公开(公告)日：2024-05-02

申请号：AU2021291163

申请日：2021-06-04

Applicant: IBM

Inventor： LI TAO ,  KANG TSUNG-SHENG ,  XIE RUILONG ,  REZNICEK ALEXANDER ,  GLUSCHENKOV OLEG

IPC: H01L27/088

Abstract: Semiconductor device designs having a buried power rail (602) with a sloped epitaxy buried contact (1702) are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate (202); source and drains (906) on opposite sides of the at least one gate, wherein at least one of the source and drains (906) has a sloped surface (1402); a buried power rail (602) embedded in the substrate (202); and a buried contact (1702) that connects the buried power rail (602) to the sloped surface (1402) of the at least one source and drain (906). Sidewall spacers (502) separate the buried power rail (602) from the substrate (202). A top of the sloped surface (1402) of the at least one source and drain (906) is above a top surface of the buried contact (1702).Methods of forming a semiconductor FET device are also provided.

公开(公告)号：SG172678A1

公开(公告)日：2011-07-28

申请号：SG2011041001

申请日：2008-12-03

Applicant: GLOBALFOUNDRIES SG PTE LTD ,  IBM ,  INFINEON TECHNOLOGIES CORP ,  SAMSUNG ELECTRONICS CO LTD

Inventor： WOH LAI CHUNG ,  WEE TEO LEE ,  PING LIU JIN ,  GLUSCHENKOV OLEG ,  UTOMO HENRY K ,  MADAN ANITA ,  LOESING RAINER ,  JIN-PING HAN ,  HYUNG-YOON CHOI

Abstract: INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONSAn integrated circuit system that includes: providing a Pl-ET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.Fig. 8

公开(公告)号：AT487234T

公开(公告)日：2010-11-15

申请号：AT05853786

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

公开(公告)号：DE10350354B4

公开(公告)日：2007-08-16

申请号：DE10350354

申请日：2003-10-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT

IPC: H01L21/316 ,  H01L21/314 ,  H01L21/318 ,  H01L21/321 ,  H01L21/336 ,  H01L29/04 ,  H01L29/78

Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.