公开(公告)号：DE3072139D1

公开(公告)日：1989-02-02

申请号：DE3072139

申请日：1980-08-12

Applicant: IBM

Inventor： BAZLEN DIETER DR ,  BOCK DIETRICH ,  GETZLAFF KLAUS J ,  HAJDU JOHANN ,  PAINKE HELMUT

IPC: G06F9/48 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/46

Abstract: In executing and controlling internal data flow for a particular program, it is often necessary to delay execution of an instruction by the insertion of an appropriate number of wait cycles. Thus, it may be necessary to interrupt instruction execution, for example, to insert a given number of wait cycles for channel access to common storage of the data processing system, for reloading a data or instruction buffer, or for a like situation. In such cases, the control unit has to ignore the particular instruction awaiting execution and execute another forced operation instead. An appropriate code is provided for a NO OPERATION instruction, say all bits zero. When a forced operation is to be executed, this code can be generated with fewer logic means at the output of the instruction register. As a result, there are no control signals active at the output of the decoder. The signals indicating forced operations have to be considered by the decoder only if a control signal is to be generated. If the control signals need be grouped for physical reasons, it is possible to determine which of these signals are a function of forced operations. This will negate the need to otherwise distribute these control signals throughout the decoder, thereby reducing and simplifying the wiring required.

公开(公告)号：CH632349A5

公开(公告)日：1982-09-30

申请号：CH1001078

申请日：1978-09-26

Applicant: IBM

Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH ROLAND ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22

公开(公告)号：AU4085678A

公开(公告)日：1980-04-24

申请号：AU4085678

申请日：1978-10-19

Applicant: IBM

Inventor： BAZLEN DIETER ,  NEUBER SIEGFRIED ,  WILLE UDO ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ

IPC: G06F9/22 ,  G06F9/16

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：DE2461410A1

公开(公告)日：1976-07-08

申请号：DE2461410

申请日：1974-12-24

Applicant: IBM DEUTSCHLAND

Inventor： HAJDU JOHANN ,  HELKE HERMANN DIPL ING ,  WOLLSCHLAEGER DIETER

IPC: G06F9/26 ,  G06F9/12

Abstract: The quari-sub-programs are entered into a control program for a data processor with micro-program control. The contents of a register define an address in a control store and for a control program with fixed addressed. The reference back-addresses for the main and sub-routines are contained in the form of an address table. An index word for releasing the main or sub-routine is stored and after the run-through of the routine the reference back-address is retirved, using the address table, with a special instruction used for tracing the routine. An instruction from the control program register may be read-in into the operational register.

公开(公告)号：FR2277376A1

公开(公告)日：1976-01-30

申请号：FR7517190

申请日：1975-05-27

Applicant: IBM

Inventor： GENG HELLMUTH R ,  HAJDU JOHANN ,  KNAUFT GUENTER

IPC: G06F7/50 ,  G06F7/505 ,  G06F7/506

公开(公告)号：CA955686A

公开(公告)日：1974-10-01

申请号：CA145363

申请日：1972-06-22

Applicant: IBM

Inventor： GENG HELLMUTH R ,  HAJDU JOHANN ,  SKUIN PETAR ,  VOGT EDWIN

IPC: G06F11/08 ,  G06F11/10 ,  H04L1/00

Abstract: In a data processing system, a first processing unit is connected to several other processing units by one transfer bus each for the two directions of transmission, a circuit arrangement for error detection being associated with the transfer lines. The first unit comprises a check character generator generating a parity check character both for the information to be transferred from the first processing unit to the further processing units and from the further processing units to the first processing unit. The transfer lines of both directions are provided with a common transfer path, by means of which the parity check characters generated by the check character generator are transferred from the first unit to the further units. Each of the further units comprises a check circuit connected to the two transfer buses and the check character transfer path and checking the correctness of the transferred information for both directions of transmission.

公开(公告)号：IT1162778B

公开(公告)日：1987-04-01

申请号：IT2585079

申请日：1979-09-20

Applicant: IBM

Inventor： HAJDU JOHANN ,  KNAUFT GUENTER

IPC: G01R31/28 ,  G01R31/3185 ,  G01T7/00 ,  G06F11/26 ,  G11C29/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C

Abstract: An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La.]. Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units. The additional circuit means facilitates and is utilized in testing the circuit integrity (stuck faults and continuity) of each minimum replaceable unit.

公开(公告)号：BR8404462A

公开(公告)日：1985-09-03

申请号：BR8404462

申请日：1984-09-05

Applicant: IBM

Inventor： CHILINSKI HERBERT ,  GETZLAFF KLAUS J ,  HAJDU JOHANN ,  RICHTER STEPHAN

IPC: G06F9/38 ,  G06F11/14 ,  G06F9/46

Abstract: In the processing of instructions in data processing systems it is not always possible to execute these instructions without interruption since particular situations, in the following called events can occur which necessitate a short interruption for executing the operations caused by such events before continuing the interrupted instruction processing. Such repetition however is only possible when the contents of the operation register containing the instruction is frozen during the interruption. Such a situation requires two actions: the first is the execution of a forced operation to resolve the event. The second action is a repetition of the instruction and execution phase of the interrupted instruction.

公开(公告)号：DE2756764A1

公开(公告)日：1979-06-21

申请号：DE2756764

申请日：1977-12-20

Applicant: IBM DEUTSCHLAND

Inventor： BLUM ARNOLD DIPL ING ,  BAZLEN DIETER DR ING ,  BERGER ROLF DIPL ING ,  BOCK DIETRICH DIPL ING ,  CHILINSKI HERBERT DIPL ING ,  GENG HELLMUTH ROLAND ,  GETZLAFF KLAUS ING GRAD ,  HAJDU JOHANN ,  RICHTER STEPHAN

IPC: G06F9/22 ,  G06F13/42 ,  G06F9/00 ,  G06F13/06

Abstract: The synchronising arrangement is for a processor and memory in an electronic data processing installation. There is a delay from the memory when data is demanded from it by the processor. A section of the arrangement has an output to the operations register of the processor for the provision of a code combination corresponding to a certain micro-instruction lasting for the duration of the memory delay. The operations decoder provides a corresponding output signal which stops the demand cycle counter. The operations register loads the next operation code existing at its input when it receives the next pulse of the system.

公开(公告)号：CA1035051A

公开(公告)日：1978-07-18

申请号：CA232796

申请日：1975-07-31

Applicant: IBM

Inventor： BLUM ARNOLD ,  HAJDU JOHANN ,  MOHR CLAUS ,  REICHL LEOPOLD ,  SONNTAG GUENTHER

IPC: G06F9/22 ,  G06F13/12 ,  G06F13/14 ,  G06F15/16 ,  G06F15/78

Abstract: Input/output registers integrated with logic and arithmetic circuits are combined externally of a processor nucleus having only storage registers, instruction decode logic, timing circuitry and arithmetic and logic unit for executing microinstructions whereby the use of the input/output registers is determined by microprogram code and by time control to either selectively execute all adapter and interface communication and control functions for input and output devices or to selectively be switched into the data flow of the processor nucleus.