公开(公告)号：DE10246306A1

公开(公告)日：2003-04-30

申请号：DE10246306

申请日：2002-10-04

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHUDZIK MICHAEL ,  GLUSCHENKOV OLEG ,  JAMMY RAJARAO ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01G4/06

Abstract: An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

公开(公告)号：WO2005122286A3

公开(公告)日：2009-04-16

申请号：PCT/US2005010825

申请日：2005-03-30

Applicant: IBM ,  BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprisisng an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be A1N or A1OxNY. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HC1/H2O2 peroxide solution.

Abstract translation: 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在半导体衬底顶部形成介电堆叠，其中包括在高k电介质顶部的绝缘夹层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极叠层。 绝缘中间层可以是AlN或AlOxNY。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包括HC1 / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：WO2007087127A3

公开(公告)日：2007-11-22

申请号：PCT/US2007000161

申请日：2007-01-03

Applicant: IBM ,  CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WANG YUN Y ,  KWONG HON WONG KEITH

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WANG YUN Y ,  KWONG HON WONG KEITH

IPC: H01L21/336

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal- oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.

Abstract translation: 提供半导体结构，例如场效应晶体管（FET）和/或金属氧化物半导体电容器（MOSCAP），其中通过将金属杂质引入到含金属的物质中来改变导电电极堆叠的功函数 材料层与导电电极一起存在于电极堆叠中。 金属杂质的选择取决于电极是否具有n型功函数或p型功函数。 本发明还提供一种制造这种半导体结构的方法。 金属杂质的引入可以通过共沉积含有金属的材料和改变金属杂质的功函数的层来形成，形成其中金属杂质层存在于含金属材料的层之间的叠层，或通过形成 包括在含金属材料上方和/或下面的金属杂质的材料层，然后加热该结构，使得金属杂质被引入到含金属的材料中。

公开(公告)号：WO0245131A3

公开(公告)日：2003-05-15

申请号：PCT/US0144626

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CHUDZIK MICHAEL ,  TEWS HELMUT ,  MCSTAY IRENE ,  KUDELKA STEPHAN ,  SETTLEMYER KENNETH ,  JAMMY RAJARAO ,  FALTERMEIER JOHNATHAN

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L27/1087 ,  H01L28/84 ,  Y10S438/964

Abstract: Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer (43) on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps (44) therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves (46) on the walls of the trench region.

Abstract translation: 提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。 一种方法包括以下步骤：在下沟槽区域的暴露壁上形成不连续的多晶硅层（43），所述不连续的多晶硅层在其中具有暴露所述衬底部分的间隙（44） 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽（46）。

公开(公告)号：WO0141201A9

公开(公告)日：2002-05-30

申请号：PCT/US0032471

申请日：2000-11-27

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： FALTERMEIER JOHNATHAN E ,  GRUENING ULRIKE ,  HEGDE SURYANARAYAN ,  JAMMY RAJARAO ,  LEE BRIAN S ,  TEWS HELMUT

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/04 ,  H01L29/12 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/28211 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/28238 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7827 ,  Y10S438/931

Abstract: A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a (100) crystal plane and a (110) crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the (110) crystal plane of the trench side wall, but not into the (100) crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

Abstract translation: 一种用于制造垂直晶体管的栅极氧化物的工艺。 在第一步骤中，在衬底中形成沟槽，沟槽从衬底的顶表面延伸并且具有沟槽底部和沟槽侧壁。 沟槽侧壁包括（100）晶面和（110）晶面。 接下来，在沟槽侧壁上形成均匀厚度的牺牲层。 在形成牺牲层之后，通过牺牲层注入氮离子，使得氮离子注入到沟槽侧壁的（110）晶面中，但不注入沟槽侧壁的（100）晶面。 然后去除牺牲层，并且沟槽侧壁被氧化以形成栅极氧化物。

公开(公告)号：AT460746T

公开(公告)日：2010-03-15

申请号：AT04812387

申请日：2004-11-29

Applicant: IBM

Inventor： CABRAL CYRIL ,  DETAVERNIER CHRISTOPHER ,  JAMMY RAJARAO ,  SAENGER KATHERINE

IPC: H01L21/8238 ,  C23C14/06 ,  C23C16/32 ,  H01L27/108 ,  H01L29/49

Abstract: A semiconductor device such as a complementary metal oxide semiconductor (CMOS) including at least one FET that includes a gate electrode including a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

公开(公告)号：DE10246306B4

公开(公告)日：2009-05-07

申请号：DE10246306

申请日：2002-10-04

Applicant: IBM ,  QIMONDA AG

Inventor： CHUDZIK MICHAEL ,  GLUSCHENKOV OLEG ,  JAMMY RAJARAO ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/8242 ,  H01G4/06 ,  H01L21/316 ,  H01L21/321

Abstract: An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

公开(公告)号：AT526684T

公开(公告)日：2011-10-15

申请号：AT05826298

申请日：2005-12-02

Applicant: IBM

Inventor： CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

IPC: H01L27/088 ,  H01L21/28 ,  H01L29/49

Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

公开(公告)号：DE60122872D1

公开(公告)日：2006-10-19

申请号：DE60122872

申请日：2001-05-02

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： WANG YUN-YU ,  JAMMY RAJARAO ,  KIMBALL J ,  KOTECKI E ,  LIAN JENNY ,  LIN CHENTING ,  MILLER A ,  NAGEL NICOLAS ,  SHEN HUA ,  WILDMAN S

IPC: H01L21/02 ,  H01L27/108 ,  H01L21/8242

Abstract: A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.

公开(公告)号：WO2006055226A3

公开(公告)日：2007-08-23

申请号：PCT/US2005039288

申请日：2005-11-01

Applicant: IBM ,  BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

Abstract translation: 提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，其条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。 本发明还提供一种制造这种结构的方法。