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    21.
    发明专利
    未知

    公开(公告)号：DE60320026D1

    公开(公告)日：2008-05-08

    申请号：DE60320026

    申请日：2003-11-21

    Applicant: IBM

    Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

    IPC: G06F12/10 ,  G06F12/12

    Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

    Method of executing microprocessor instructions, associated microprocessor and data processing system.
    24.
    发明专利
    Method of executing microprocessor instructions, associated microprocessor and data processing system. 未知

    公开(公告)号：HK1037248A1

    公开(公告)日：2002-02-01

    申请号：HK01106811

    申请日：2001-09-27

    Applicant: IBM

    Inventor： KAHLE JAMES ALLAN ,  MOORE CHARLES ROBERTS

    IPC: G06F9/06 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F

    Abstract: A processor and data processing system suitable for dispatching an instruction to an issue unit. The issue unit includes a primary issue queue and a secondary issue queue. The instruction is stored in the primary issue queue if the instruction is currently eligible to issue for execution. The instruction is stored in the secondary issue queue if the instruction is currently ineligible to issue for execution. An instruction may be moved from the primary issue queue to the secondary issue queue if instruction is dependent upon results from another instruction. In one embodiment, the instruction may be moved from the primary issue queue to the secondary issue queue after issuing the instruction for execution. In this embodiment, the instruction may be maintained in the secondary issue queue for a specified duration. Thereafter, the secondary issue queue entry containing the instruction is deallocated if the instruction has not been rejected.

    25.
    发明专利
    未知

    公开(公告)号：BR9403859A

    公开(公告)日：1995-06-20

    申请号：BR9403859

    申请日：1994-09-26

    Applicant: IBM

    Inventor： KAHLE JAMES ALLAN

    IPC: G06F9/312 ,  G06F9/38 ,  G06F12/08 ,  G06F13/16

    Abstract: An information processing system 10 includes a processor 10 for processing instructions, a system memory 30, a cache memory 12, and a supplemental 26. In response to a first instruction, the supplemental memory stores first information from a system memory. In response to a second instruction, the cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise.

    26.
    发明专利
    未知

    公开(公告)号：BR9000112A

    公开(公告)日：1990-10-23

    申请号：BR9000112

    申请日：1990-01-12

    Applicant: IBM

    Inventor： GROHOSKI GREGORY FREDERICK ,  KAHLE JAMES ALLAN ,  NGUYENPHU MYHONG ,  RAY DAVID SCOTT

    IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48 ,  G06F15/80

    Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

    29.
    发明专利
    未知

    公开(公告)号：FR2800482B1

    公开(公告)日：2003-06-13

    申请号：FR0011605

    申请日：2000-09-12

    Applicant: IBM

    Inventor： KAHLE JAMES ALLAN ,  LE HUNG QUI ,  MOORE CHARLES ROBERTS

    IPC: G06F9/38 ,  G06F15/04

    Abstract: A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of instructions into an instruction group. The dispatch and completion logic assigns a group tag to the instruction group and records the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. The dispatch and control logic may record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. The processor may flush the instruction group in response to detecting an exception generated by an instruction in the instruction group.

    30.
    发明专利
    未知

    公开(公告)号：ES2176225T3

    公开(公告)日：2002-12-01

    申请号：ES94306614

    申请日：1994-09-08

    Applicant: IBM

    Inventor： KAHLE JAMES ALLAN

    IPC: G06F9/312 ,  G06F9/38 ,  G06F12/08

    Abstract: An information processing system 10 includes a processor 10 for processing instructions, a system memory 30, a cache memory 12, and a supplemental 26. In response to a first instruction, the supplemental memory stores first information from a system memory. In response to a second instruction, the cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise.

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