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    21.
    发明专利
    未知

    公开(公告)号：AT144870T

    公开(公告)日：1996-11-15

    申请号：AT93480087

    申请日：1993-06-30

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  MAUDUIT DANIEL ,  PAUPORTE ANDRE ,  SPAGNOL VICTOR ,  LEBIZAY GERALD ,  MUNIER JEAN-MARIE ,  SAINT-GEORGES ERIC

    IPC: H04L29/06

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

    INPUT/OUTPUT PORT CONTROL
    25.
    发明专利
    INPUT/OUTPUT PORT CONTROL 未知

    公开(公告)号：CA1030267A

    公开(公告)日：1978-04-25

    申请号：CA225414

    申请日：1975-04-22

    Applicant: IBM

    Inventor： LEBIZAY GERALD ,  KERRIGAN MICHAEL ,  MAC SORLEY OLIN L ,  WEISS ALFRED

    IPC: G06F13/36 ,  G06F13/34

    Abstract: An input-output port control subsystem for use with a computer system having separate source and destination buses incorporated therein. Said system including circuitry for controlling operations of said system and said input/output subsystem, said subsystem including a bidirectional input/output bus for transferring data to and from said system, and separate gating means for selectively connecting said source and destination buses to said bidirectional I/O bus. External devices are connected to said bus thru an adaptor unit which is directly connected to said processing system by appropriate control lines. The input/output subsystem is adapted to operate either under programmed I/O control mode thru the central processing system or in cycle steal mode wherein the I/O devices themselves request cycle steal service time on the I/O bus thru their connected adaptor.

    27.
    发明专利
    未知

    公开(公告)号：DE2504288A1

    公开(公告)日：1975-09-11

    申请号：DE2504288

    申请日：1975-02-01

    Applicant: IBM

    Inventor： HAIMS MURRAY J ,  HAO HSIEH TUNG ,  LEBIZAY GERALD ,  WEISS ALFRED

    IPC: G06F7/501 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506

    Abstract: 1466366 Parallel binary adders INTERNATIONAL BUSINESS MACHINES CORP 5 Feb 1975 [7 March 1974] 4874/75 Heading G4A A parallel binary adder comprises registers 30, 31 which initially respectively store an augend A and an addend B, the quantitites A, B being gated 33, 34 to an exclusive-OR circuit 32 where the quantity A#B is generated and stored (overwriting A) in register 30 via a gate 35, the quantities A#B and B then being gated 37, 38 to a carry generation circuit 36 which generates a carry C therefrom, the quantities A#B and C then being gated 33, 39 to the exclusive-OR circuit 32 which generates the sum S = (A#B)# C therefrom and stores the sum S in register 30. The carry generation circuit 36 may be implemented in AND/OR/NOT logic (Fig. 1, not shown) and operates using Boolean algorithms given in the Specification to simultaneously generate two carries C k-1 , C k from a lower order carry C k+1 . In a second embodiment of the carry generation circuit 36, Fig. 2 (not shown), NOR logic functionally equivalent to Fig. 1 is used to facilitate its implementation as a LSI circuit, the inverses C k-1 , C k of the carries being simultaneously generated from the lower order carry C k+1 .

    DATA TRANSFER DEVICE
    28.
    发明专利
    DATA TRANSFER DEVICE 未知

    公开(公告)号：GB1277795A

    公开(公告)日：1972-06-14

    申请号：GB4460069

    申请日：1969-09-10

    Applicant: IBM

    Inventor： LEBIZAY GERALD ,  GUILLOU JOSEPH CHARLES ,  DUVOCHEL HENRI PIERRE ,  POTOCKI JEAN ZDZISLAW

    IPC: G06F13/38 ,  H04L13/08

    Abstract: 1277795 Digital transmission systems INTERNATIONAL BUSINESS MACHINES CORP 10 Sept 1969 [24 Sept 1968] 44600/69 Heading H4P In a system for transferring data between a store and a number of lines which operate at different speeds and in different modes (e.g. synchronous or start-stop) each line is scanned at least once during a scan cycle. The cycle is divided into a number of segments, a number of lines being scanned sequentially during each segment. The order of scan is determined by group control words GCW. A GCW controls the sequential scanning of a group of lines having the same mode and speed. Each GCW accesses a number of line control words LCW in each of which data sent to/from the corresponding line is disassembled/assembled. At the start of a scan cycle the first GCW of a segment is read from a store address determined by a group control address register GCAR. The GCW indicates which line is to be scanned and accesses the corresponding LCW. A bit or sample is passed to/from the LCW from/to the line. Counts stored in the GCW are incremented to indicate the address of the next LCW and the next line to be scanned. Another count is decremented to indicate how many more lines are to be scanned. If the latter is not zero the next line is scanned as above, but if it is zero and the GCW does not show that it is the last of the present segment the GCAR is incremented to extract the next GCW from the store and scanning of the next group of lines proceeds as above. However, if the GCW is the last of the segment a count representing idle steps in the segment (i.e. steps in not allocated to line scanning and hence available for other machine operations) is counted to zero. If the GCAR shows that there is a further segment to be scanned it is incremented and the first GCW of the next segment is read from the store for further scanning as above. On the other hand, if there is no further segment to be scanned the whole scan cycle is now repeated. When a character to be transmitted has been assembled in the LCW it is placed in a shift register at the line's transmitter. A counter is incremented each time the line is scanned, and the count is compared with a number (from the GCW) which tells how many times the line must be scanned in each bit duration. After this number of scans the shift register content is shifted one step and the counter reset. This continues until the whole character has been read out to the line. Start and Stop bits are added if required. When the register is empty the next character from the LCW is passed to it. During reception the GCW indicates after how many steps the line must be sampled (normally mid-bit), the sample being stored in a shift register and passed to the LCW. When the register is full the character is passed to another storage area in the LCW for delivery to the store.

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