公开(公告)号：WO03025977A3

公开(公告)日：2003-08-14

申请号：PCT/US0230369

申请日：2002-09-17

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78618

Abstract: The present invention relates to a wrapped-gate transistor including a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions (28) are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer (40) is formed on the substrate. A gate electrode (42) is formed on the gate dielectric layer (40) to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric (40) therebetween. The substrate is a silicon island (12) formed on an insulation layer of an SOI (silicon-on-insulator) substrate or a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions (28) are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the "body-to-source" voltage.

Abstract translation: 本发明涉及包括具有上表面和彼此相对的第一和第二侧表面的衬底的缠绕栅极晶体管。 源极和漏极区域（28）形成在衬底中，其间具有沟道区域。 沟道区域从衬底的第一侧表面延伸到第二侧表面。 栅极电介质层（40）形成在衬底上。 栅极电极（42）形成在栅极电介质层（40）上，以从上表面和第一和第二侧表面覆盖沟道区域，栅电介质（40）位于它们之间。 衬底是形成在SOI（绝缘体上硅）衬底或常规非SOI衬底的绝缘层上的硅岛（12），并且具有包括第一和第二侧表面的四个侧表面。 源极和漏极区域（28）形成在与第一和第二侧表面垂直的第三和第四侧表面相邻的基板的部分上。 包封门结构在通道区域内提供了更好更快的电位控制，从而产生陡峭的次阈值斜率和对“体对电压”电压的低灵敏度。

公开(公告)号：AT519228T

公开(公告)日：2011-08-15

申请号：AT00103964

申请日：2000-02-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L27/108 ,  H01L21/8242

Abstract: A semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. A deep trench fill fills each deep trench. A buried strap extends completely across each deep trench over each deep trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.

公开(公告)号：CZ20011964A3

公开(公告)日：2001-11-14

申请号：CZ20011964

申请日：1999-11-26

Applicant: IBM

Inventor： AGAHI FARID ,  HSU LOUIS ,  MANDELMAN JACK

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the. second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.

公开(公告)号：DE602006018643D1

公开(公告)日：2011-01-13

申请号：DE602006018643

申请日：2006-10-27

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  MANDELMAN JACK ,  TONTI WILLIAM

IPC: H01L23/525

公开(公告)号：AT441938T

公开(公告)日：2009-09-15

申请号：AT06830385

申请日：2006-12-05

Applicant: IBM

Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  HSU LOUIS ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/78

Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

公开(公告)号：AT377841T

公开(公告)日：2007-11-15

申请号：AT02791319

申请日：2002-11-25

Applicant: IBM

Inventor： DORIS BRUCE ,  CHIDAMBARRAO DURESETI ,  IEONG MEIKEI ,  MANDELMAN JACK

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

公开(公告)号：AU2002343408A1

公开(公告)日：2003-04-01

申请号：AU2002343408

申请日：2002-09-17

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119 ,  H01L31/113

Abstract: A wrapped-gate transistor includes a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer is formed on the substrate. A gate electrode is formed on the gate dielectric layer to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric therebetween. The substrate is a silicon island formed on an insulation layer of an SOI (silicon-on-insulator) substrate or on a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the "body-to-source" voltage.

公开(公告)号：DE10307822B4

公开(公告)日：2005-08-18

申请号：DE10307822

申请日：2003-02-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  DIVAKARUNI RAMACHANDRA ,  BEINTNER JOCHEN ,  MANDELMAN JACK

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8239

Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

公开(公告)号：AU2002351206A1

公开(公告)日：2004-06-23

申请号：AU2002351206

申请日：2002-12-03

Applicant: IBM

Inventor： VOLDMAN STEVEN H ,  MANDELMAN JACK

IPC: H01L21/336 ,  H01L23/62 ,  H01L27/02 ,  H01L27/12 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01

公开(公告)号：PL348501A1

公开(公告)日：2002-05-20

申请号：PL34850199

申请日：1999-11-26

Applicant: IBM

Inventor： AGAHI FARID ,  HSU LOUIS ,  MANDELMAN JACK

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the. second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.