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    21.
    发明专利
    未知

    公开(公告)号：DE69933610D1

    公开(公告)日：2006-11-30

    申请号：DE69933610

    申请日：1999-05-06

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  REVIL NATHALIE

    IPC: H01L23/525

    Abstract: An IC fuse (20) has central branch arms (22, 23) intersecting at a current focusing zone (24) for local current density increase to facilitate fuse blowing. An IC fuse (20), formed by etching a polysilicon or metal layer, comprises central tracks (21) of which the ends include areas (32, 33, 35, 36) provided with electrical contacts (40, 41) to which is applied a potential difference for blowing the fuse. The novelty is that the central tracks (21) form two or more shunt-connected arms (22, 23) intersecting at a zone (24) forming a blowing current focal point to facilitate fuse blowing by increasing the local current density. An Independent claim is also included for an IC including the above fuse.

    22.
    发明专利
    未知

    公开(公告)号：DE60307174D1

    公开(公告)日：2006-09-14

    申请号：DE60307174

    申请日：2003-05-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  CREMER SEBASTIEN ,  MARTY MICHEL

    IPC: H01L21/02 ,  H01L23/522

    Abstract: Capacitor is manufactured in substrate (1) by digging recess into substrate; forming first conformal layer of insulating material; forming second conductive layer; forming third layer of conductive or insulating material filling up recess; digging trenches into third layer, across entire height; depositing fourth layer of conductive material; forming fifth layer of dielectric material; and depositing sixth layer of conductive material. An Independent claim is also included for a capacitor formed in a substrate comprising: (a) a recess (2) dug into a substrate; (b) a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; (c) a second layer of a conductive material covering the first layer; (d) a third layer of a conductive or insulating material filling the recess; (e) trenches crossing the third layer; (f) a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges; (g) a fifth layer of a dielectric material covering the fourth layer; and (h) a sixth layer of a conductive material covering the fifth layer.

    23.
    发明专利
    未知

    公开(公告)号：DE69928673D1

    公开(公告)日：2006-01-05

    申请号：DE69928673

    申请日：1999-05-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  REVIL NATHALIE

    IPC: G03F1/00 ,  G03F7/20 ,  H01L21/033 ,  H01L23/525

    Abstract: The implementation by photolithography of integrated circuit includes at least one fuse (20) comprising pads (3,4) for electrical contacts and a central region (2) substantially in the form of a bar with a thinner region (21) forming a weak point facilitating the breakdown of fuse element by increasing current density in the conditions of standard breakdown. The method comprises the following steps: the formation of an exposition mask reproducing the fuse design (D20) comprising a central region (D2) in the form of a bar, and artificial elements (D22, D23) in the neighbourhood of central region; the formation of etching mask by exposition for the fuse (20) having the central region (2) with the appearance of a thinner region (21) by the optical effect of proximity, so that the width (W2) of thin region is less than the technological minimum (Wmin) determined by the manufacturing method for integrated circuit. Each artificial element (D22, D23) has an edge (D22-1, D23-1) located with respect to the central region (D2) at a distance (DE3), which is less than the technological threshold (SEmin), below which the optical effect of proximity is manifested. The central region (D2) has a width (DW1) chosen so to obtain the width (W1) of fuse (20) substantially equal to the technological minimum (Wmin). The width (W2) of thin region is substantially equal to half the average width (W1) of central region on the outside of thin zone. The optical effect of proximity forms a progressive thinning of central region, and also transitions of thinning with oblique edges. The thinning is by the formation of notches (21-1, 21-2) on the sides of central region. The etching mask has at least one opening greater than the spacing between elements in the fuse design exposition mask. The etching mask is obtained by the deposition of a layer of photosensitive resin onto a layer of integrated circuit, following an exposition step and a step for the resin removal by a solvent. The fuse of integrated circuit is implemented by the etching of a thin layer of polysilicon, metal or alloy, or by etching of a thin layer formed by a pile of metals or alloys. The fuse of integrated circuit is implemented by polysilicon silicide, with a metal as eg. titanium, cobalt, tungsten, tantalum, and the method includes a step of etching in plasma. The implementation of artificial elements (22,23) favours the etching of an oxide layer on the sides of fuse, so that the fuse has oxide spacers which do not cover entirely the sides of thin zone.

    25.
    发明专利
    未知

    公开(公告)号：FR2783093B1

    公开(公告)日：2000-11-24

    申请号：FR9811221

    申请日：1998-09-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  ROBILLIART ETIENNE ,  DUTARTRE DIDIER

    IPC: H01L21/02 ,  H01L29/92

    Abstract: Built-in capacitance (C1) on a silicon substrate (7) comprises a first highly doped polysilicon electrode (1), a thin layer (3) of silicon oxide, a second polysilicon electrode (10) and a silicide layer (4) over the second electrode. The second electrode has a high dopant concentration at the interface with the silicon oxide and a relatively low dopant concentration at the interface with the silicide layer. An Independent claim is also included for an integrated circuit, comprising at least one capacitance as above.

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