公开(公告)号：FR3009629A1

公开(公告)日：2015-02-13

申请号：FR1357901

申请日：2013-08-08

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： FREY LAURENT ,  MARTY MICHEL

IPC: G02B5/28 ,  H01L27/146 ,  H01L31/0232

Abstract: Procédé de réalisation d'un filtre optique multicouches au sein d'un circuit intégré, comprenant un substrat, une partie d'nterconnexion (ITCI, ITCS), la réalisation du filtre optique comprenant une formation d'une première partie de filtre (FL1) à l'intérieur de la partie d'nterconnexion au dessus d'une zone photosensible située dans le substrat, et une formation d'une deuxième partie de filtre (FL2) au dessus de la première partie de filtre et de la partie d'interconnexion. L'invention a également pour objet un circuit intégré comprenant un filtre optique.

公开(公告)号：FR2955205A1

公开(公告)日：2011-07-15

申请号：FR0959060

申请日：2009-12-16

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  ROY FRANCOIS ,  BESSON PASCAL ,  PRIMA JENS

IPC: H01L27/14 ,  H01L21/20 ,  H01L21/302 ,  H01L21/768 ,  H01L21/77 ,  H01L23/48

Abstract: Procédé de réalisation d'un dispositif microélectronique comprenant une réalisation d'un premier substrat (1) semiconducteur comportant une formation d'une première couche (5) et d'une deuxième couche (4) entre une première face (7) et une deuxième face (2) du substrat, une réalisation de premiers composants (10) et d'une partie d'interconnexion au niveau et au dessus de la deuxième face (2), un amincissement du substrat comprenant une première gravure sélective du premier substrat depuis la première face (7) avec arrêt sur la première couche (5) suivie d'une deuxième gravure sélective avec arrêt sur la deuxième couche (4).

公开(公告)号：FR2928490A1

公开(公告)日：2009-09-11

申请号：FR0851494

申请日：2008-03-07

Applicant: ST MICROELECTRONICS SA

Inventor： COUDRAIN PERCEVAL ,  CORONEL PHILIPPE ,  MARTY MICHEL ,  BOPP MATTHIEU

IPC: H01L21/00 ,  H01L31/0232

Abstract: L'invention concerne une structure semiconductrice comprenant une première zone active (R) sous laquelle est enterrée une première couche réfléchissante (32) et au moins une deuxième zone active (G) sous laquelle est enterrée une deuxième couche réfléchissante (34), caractérisée en ce que la surface supérieure de la deuxième couche réfléchissante est plus proche de la surface supérieure de la structure que la surface supérieure de la première couche réfléchissante.

公开(公告)号：DE69836657D1

公开(公告)日：2007-02-01

申请号：DE69836657

申请日：1998-06-25

Applicant: ST MICROELECTRONICS SA

Inventor： JAOUEN HERVE ,  MARTY MICHEL

IPC: G02B6/42 ,  H01L33/00 ,  H01L27/14 ,  H01L31/0232

公开(公告)号：DE60307174D1

公开(公告)日：2006-09-14

申请号：DE60307174

申请日：2003-05-15

Applicant: ST MICROELECTRONICS SA

Inventor： DELPECH PHILIPPE ,  CREMER SEBASTIEN ,  MARTY MICHEL

IPC: H01L21/02 ,  H01L23/522

Abstract: Capacitor is manufactured in substrate (1) by digging recess into substrate; forming first conformal layer of insulating material; forming second conductive layer; forming third layer of conductive or insulating material filling up recess; digging trenches into third layer, across entire height; depositing fourth layer of conductive material; forming fifth layer of dielectric material; and depositing sixth layer of conductive material. An Independent claim is also included for a capacitor formed in a substrate comprising: (a) a recess (2) dug into a substrate; (b) a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; (c) a second layer of a conductive material covering the first layer; (d) a third layer of a conductive or insulating material filling the recess; (e) trenches crossing the third layer; (f) a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges; (g) a fifth layer of a dielectric material covering the fourth layer; and (h) a sixth layer of a conductive material covering the fifth layer.

公开(公告)号：FR2858877A1

公开(公告)日：2005-02-18

申请号：FR0350418

申请日：2003-08-11

Applicant: ST MICROELECTRONICS SA

Inventor： MARTINET BERTRAND ,  MARTY MICHEL ,  CHEVALIER PASCAL ,  CHANTRE ALAIN

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737

Abstract: A method for forming a heterojunction bipolar transistor including the steps of: forming in a semiconductor substrate a collector area of a first doping type; growing by epitaxy above a portion of the collector area a silicon/germanium layer of a second doping type forming a base area; forming above the silicon/germanium layer a sacrificial emitter formed of a material selectively etchable with respect to the silicon/germanium layer and with respect to the layers and consecutively-formed insulating spacers; forming first insulating spacers on the sides of the sacrificial emitter; growing by epitaxy a silicon layer above the exposed portions of the silicon/germanium layer; forming second insulating spacers adjacent to the first spacers and laid on the silicon layer; covering the entire structure with an insulating layer; partially removing the insulating layer above the sacrificial emitter and removing the sacrificial emitter; filling the space previously taken up by the sacrificial emitter with a semiconductor material of the first doping type.

公开(公告)号：FR2845522A1

公开(公告)日：2004-04-09

申请号：FR0212278

申请日：2002-10-03

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  CORONEL PHILIPPE ,  LEVERD FRANCOIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/417 ,  H01L29/732 ,  H01L21/74

Abstract: An integrated circuit incorporates a buried layer of the type with conductivity determined in a plane essentially parallel to a plane of a main surface of the circuit. The median part of this buried layer (23, 24) is filled with a metallic type material (29). An Independent claim is also included for a method for the formation of a layer buried in a semiconductor substrate of an integrated circuit.

公开(公告)号：FR2813707A1

公开(公告)日：2002-03-08

申请号：FR0011419

申请日：2000-09-07

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  CHANTRE ALAIN ,  MARTY MICHEL ,  JOUAN SEBASTIEN

IPC: H01L21/331 ,  H01L29/10 ,  H01L21/28

Abstract: Fabrication of a bipolar transistor on a monocrystalline silicon substrate (1) with a first type of conductivity incorporates a stage of carbon implantation at the surface of the substrate followed by annealing, before epitaxial formation of the base of the transistor in the form of a multi-layer (T) semiconductor incorporating at least one lower layer (4), a median heavily doped layer (5) with a second type of conductivity and a upper layer (6) which contacts a heavily doped emitter (9) with the first type of conductivity. An Independent claim is included for a hetero-junction bipolar transistor produced.

公开(公告)号：FR2803091B1

公开(公告)日：2002-03-08

申请号：FR9916283

申请日：1999-12-22

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  FELLOUS CYRIL

IPC: H01L21/223 ,  H01L21/331 ,  H01L21/8222

公开(公告)号：FR2811473A1

公开(公告)日：2002-01-11

申请号：FR0008686

申请日：2000-07-04

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  BAUDRY HELENE ,  LEVERD FRANCOIS

IPC: H01L21/316 ,  H01L21/762 ,  H01L21/763 ,  H01L21/331 ,  H01L21/306

Abstract: Prior to the implementation of transistors, one configures within the substrate a deep insulated drain following the configuration within the substrate of a less deep insulated drain lengthening the deep drain. The configuration of the deep drain includes a coating of the internal walls of the drain by an initial layer of oxide (100) obtained by a rapid thermal oxidation and a filling of the drain with polysilicon (120) inside an envelope formed with an insulating material (101). The configuration of the less deep drain also includes a coating of the internal walls with an initial oxide layer (15) obtained by rapid thermal oxidation and a filling with an insulating material (16, 17). An Independent claim is also included for an integrated circuit incorporating within a substrate some insulating deep drain and less deep drain regions separating the transistors.