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    22.
    发明专利
    未知

    公开(公告)号：DE69812369D1

    公开(公告)日：2003-04-24

    申请号：DE69812369

    申请日：1998-12-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  OTTINI DANIELE ,  SAVO ALESSANDRO

    IPC: G11B20/10 ,  G11B20/00 ,  H03M1/10 ,  H03M1/12 ,  H04L27/08

    Abstract: A read and analog-to-digital data conversion channel comprising preamplifying circuits (Pre-Amp), automatic gain control circuits (VGA), harmonics filters (MRA), equalizing low pass filters (LPF), a time interleaved analog-to-digital converter (INTERLEAVED ATOD) including a pair of identical analog/digital converters (ATOD_EVEN, ATOD_ODD) functioning in parallel and at a half clock frequency, subdividing the signal path into two parallel paths through said two identical converters, one for even bits and the other for odd bits, and a digital post-processing block (DIGITAL Post Processing) fed by two output streams of said time interleaved converter (INTERLEAVED ATOD) and outputting a reconstructed data stream (DATA) and controlling said circuits, through dedicated digital-to-analog converters (DAC_VGA, DAC_MRA, DAC_FC, DAC_BOOST), means for compensating the offset of the digital-to-analog converters contained in said pair of identical analog-to-digital converters (ATOD_EVEN, ATOD_ODD) of said time interleaved converter (INTERLEAVED ATOD), controlled by said post-processing block (DIGITAL Post Processing) through a digital-to-analog converter, further comprises two distinct offset compensating circuits, each composed of an offset compensating stage (OFFSET_EVEN_STAGE, OFFSET_ODD_STAGE) independently controlled by said digital post-processing block through a dedicated digital-to-analog converter (DAC_OFF_E, DAC_OFF_O), preventing appearance of spurious patterns in frequency domain.

    23.
    发明专利
    未知

    公开(公告)号：DE69614501T2

    公开(公告)日：2002-04-11

    申请号：DE69614501

    申请日：1996-03-08

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  DEMICHELI MARCO ,  PISATI VALERIO

    IPC: H03L7/099 ,  H03B1/00

    Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.

    24.
    发明专利
    未知

    公开(公告)号：DE69803856D1

    公开(公告)日：2002-03-21

    申请号：DE69803856

    申请日：1998-11-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OTTINI DANIELE ,  BRUCCOLERI MELCHIORRE ,  BOLLATI GIACOMINO ,  DEMICHELI MARCO

    IPC: H03M1/36 ,  H03M1/08 ,  H03M1/12 ,  H03M7/16

    Abstract: A flash analog-to-digital converter comprising a bank of comparators (COMPi) with a differential output, generating a thermometric code and a bank of three-input (A,B,C) logic NOR gates (NORj) for correcting errors in said thermometric code, has enhanced immunity to noise and reduced imprecisions, especially at high conversion rates upon occurence of metastability within the comparators, by providing for a passive interface constituted by a plurality of voltage dividers (Ra-Rb), each connected between the noninverted output (out_p) of a respective comparator (COMPi) and the inverted output (out_n) of the comparator of higher order (COMPi+1) of said bank; a corresponding logic NOR gate (NORj) of said bank having a first input (A) coupled to the inverted output (out_n) of said respective comparator (COMPi-1), a second input (B) coupled to the noninverted output (out_p) of said comparator (COMPi) of higher order and a third input (C) coupled to an intermediate tap of said voltage divider (Ra-Rb).

    26.
    发明专利
    未知

    公开(公告)号：DE69520562T2

    公开(公告)日：2001-07-12

    申请号：DE69520562

    申请日：1995-05-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE ,  PISATI VALERIO

    IPC: H03M1/68 ,  G06J1/00 ,  H03M1/66 ,  H03M1/78 ,  H03M1/00

    Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

    27.
    发明专利
    未知

    公开(公告)号：DE69604647T2

    公开(公告)日：2000-01-27

    申请号：DE69604647

    申请日：1996-05-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CUSINATO PAOLO ,  BRUCCOLERI MELCHIORRE

    IPC: H03K3/013 ,  H03K3/03 ,  H03L7/099 ,  H03L7/183

    Abstract: Voltage-controlled oscillator, with high noise rejection of the supply voltage, of the type constituted by a plurality of delay cells (21, 22, 23) in an odd number N ≥3, which are connected to form a first ring oscillator (27, 34) and powered by the difference between a supply voltage Vcc and a variable regulating voltage VR, comprising at least one second ring oscillator (28, 46) formed by a plurality of delay cells (23, 24, 25) in an odd number M ≥3, at least one of which is also a delay cell of the first oscillator (27, 34) and at least two of which (24, 25) do not belong to the first oscillator, at least one of these two cells (24, 25) being powered by a constant voltage (Vcc), in such a manner that the two oscillators operate at the same frequency and the interaction between the two oscillators introduces a high-frequency negative feedback which has the effect of effectively reducing the noise of the supply voltage Vcc.

    28.
    发明专利
    未知

    公开(公告)号：DE69604647D1

    公开(公告)日：1999-11-18

    申请号：DE69604647

    申请日：1996-05-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CUSINATO PAOLO ,  BRUCCOLERI MELCHIORRE

    IPC: H03K3/013 ,  H03K3/03 ,  H03L7/099 ,  H03L7/183

    Abstract: Voltage-controlled oscillator, with high noise rejection of the supply voltage, of the type constituted by a plurality of delay cells (21, 22, 23) in an odd number N ≥3, which are connected to form a first ring oscillator (27, 34) and powered by the difference between a supply voltage Vcc and a variable regulating voltage VR, comprising at least one second ring oscillator (28, 46) formed by a plurality of delay cells (23, 24, 25) in an odd number M ≥3, at least one of which is also a delay cell of the first oscillator (27, 34) and at least two of which (24, 25) do not belong to the first oscillator, at least one of these two cells (24, 25) being powered by a constant voltage (Vcc), in such a manner that the two oscillators operate at the same frequency and the interaction between the two oscillators introduces a high-frequency negative feedback which has the effect of effectively reducing the noise of the supply voltage Vcc.

    30.
    发明专利
    未知

    公开(公告)号：ITUB20154605A1

    公开(公告)日：2017-04-12

    申请号：ITUB20154605

    申请日：2015-10-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RADICE FRANCESCO ,  BRUCCOLERI MELCHIORRE ,  ZUFFADA MAURIZIO

    IPC: H03F1/08 ,  H03F1/42 ,  H03F3/08 ,  H03F3/45 ,  H03F3/72

    Abstract: A transimpedance amplifier includes a first and a second power supply terminal for receiving a positive constant supply voltage, wherein the second power supply terminal represents a ground, and an input terminal adapted to be connected to a current source. The transimpedance amplifier further comprises a transistor comprising a control terminal and two further terminals, wherein the input terminal is connected to the control terminal of the first transistor. An inductor is connected between the first of the two further terminals of the transistor and the first power supply terminal, and a bias network is connected between the second of the two further terminals of the transistor and ground. Specifically, the transimpedance amplifier is configured such that the resistance between said first of said two further terminals of said first transistor and said first power supply terminal is small enough, such that said transimpedance amplifier operates as a differentiator.

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