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    21.
    发明专利
    未知

    公开(公告)号：DE69624230T2

    公开(公告)日：2003-02-13

    申请号：DE69624230

    申请日：1996-07-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  ZANARDI STEFANO ,  GOLLA CARLA

    IPC: H03K19/003 ,  H03K17/00

    Abstract: An output stage (1) for electronic circuits (2) with high voltage tolerance and of the type comprising an output buffer made up of a complementary transistor pair (Pu,Nu) comprising a P-channel MOS pull-up transistor (Pu) and an N-channel MOS pull-down transistor. The transistors are connected together to make up an output terminal (U) of the stage which comprises in addition a switch (6) having an input (8) connected to the output terminal (U) of the stage and an output (9) connected to the control terminal of the pull-up transistor to drive said control terminal in a state of extinction of the output buffer.

    23.
    发明专利
    未知

    公开(公告)号：DE69428423T2

    公开(公告)日：2002-06-20

    申请号：DE69428423

    申请日：1994-02-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA ,  PADOAN SILVIA ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/14 ,  G11C16/16

    Abstract: A regulating circuit for discharging non-volatile memory cells (5) in an electrically programmable memory device, of the type which comprises: at least one switch connected between a programming voltage reference (VPP) and a line (SCR) shared by the source terminals of the transistors forming said memory cells (5), and at least one discharge connection between said common line (SCR) to the source terminals and a ground voltage reference (GND), further comprises a second connection to ground of the line (SCR) in which a current (Is) generator (G) is connected and a normally open switch (I1). Also provided is a logic circuit (3) connected to the line (SRC) to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch (I1) to make. This solution allows a slow discharging phase of the line (SRC) to be effected at the end of the erasing phase.

    24.
    发明专利
    未知

    公开(公告)号：DE69328253T2

    公开(公告)日：2000-09-14

    申请号：DE69328253

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MACCARRONE MARCO ,  OLIVO MARCO ,  GOLLA CARLA ,  PADOAN SILVIA

    IPC: G11C5/14 ,  G11C16/06 ,  G11C17/00 ,  G11C16/30

    Abstract: A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage (4) being powered between a first (VPP) and a second (GND) voltage reference and having a first input terminal connected to a resistive divider (2) of the first reference voltage (VPP) and an output terminal fed back to said input through a current mirror (3), and a source-follower transistor (MOUT) controlled by the output and connected to the cells through a programming line (VP). Also provided is a MOS transistor (MG2) which connects to ground the programming line (VP) and a corresponding resistive path (7) connected between the current mirror (3) and the second voltage reference (GND).

    25.
    发明专利
    未知

    公开(公告)号：DE69222626T2

    公开(公告)日：1998-02-05

    申请号：DE69222626

    申请日：1992-04-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA ,  SALI MAURO L

    IPC: H03H21/00 ,  H03H17/02 ,  H03H17/06

    Abstract: A high-resolution digital filter of a type which comprises a memory structure receiving as input a sampled digital signal, and an adder chain with delay blocks therebetween, the adders being connected to memory outputs to convert the input signal into an output signal having predetermined frequency response characteristics, has the memory structure made up of at least one pair of non-volatile memories (3,4) being input each one portion (x(n)1,x(n)2) only of the sampled signal.

    26.
    发明专利
    未知

    公开(公告)号：DE69935919D1

    公开(公告)日：2007-06-06

    申请号：DE69935919

    申请日：1999-12-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZAMMATTIO MATTEO ,  MOTTA ILARIA ,  MICHELONI RINO ,  GOLLA CARLA

    IPC: G11C16/30 ,  G11C5/14

    Abstract: A voltage boost device includes a first boost stage (4) and a second boost stage (5) connected to an input terminal and to an output terminal (10), the output terminal (10) supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal (SB) having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage (4) is enabled in presence of the second logic level of the operating condition signal (SB), and is disabled in presence of the first logic level of the operating condition signal (SB); the second boost stage (5) is controlled in a first operating condition in presence of the first logic level of the operating condition signal (SB), and is controlled in a second operating condition in presence of the second logic level of the operating condition signal (SB).

    27.
    发明专利
    未知

    公开(公告)号：DE69622149D1

    公开(公告)日：2002-08-08

    申请号：DE69622149

    申请日：1996-03-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRANCHETTI MAURIZIO ,  CONCI ARMANDO ,  GOLLA CARLA

    IPC: G06F11/10

    Abstract: The invention relates to a method of recovering faulty non-volatile memories. This method can be applied to an electrically programmable semiconductor non-volatile memory device being set up as a multi-sectors memory matrix and including selection circuitry for selecting words or individual bytes of the memory. According to this method, the memory matrix is addressed by byte, rather than by memory word, by acting said selection circuitry, whenever the device fails an operation test. The use of a Hamming code of error correction to remedy malfunctions due to manufacture allows the method to be applied to those devices which fail their test and would otherwise be treated as rejects.

    29.
    发明专利
    未知

    公开(公告)号：DE69325277T2

    公开(公告)日：2000-01-20

    申请号：DE69325277

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PADOAN SILVIA ,  OLIVO MARCO ,  GOLLA CARLA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

    Abstract: A circuit for detecting a threshold voltage in storage devices integrated to a semiconductor, for which a power supply above a certain value is provided, is of the type which comprises a comparator (3) connected between a voltage supply line (2) and a signal ground (GND) and having a first or reference input (I1) and a second or signal input (I2), and comprises a generator (8) of a stable voltage reference (RIF) having an output connected to the first input (I1) and a divider (9) of a supply voltage (Vdd) connected to the second input (I2) of the comparator (3). A circuit means is arranged to feed the voltage line (2) with the higher of the supply voltage (Vdd) value and the value of a programming voltage (Vpp) of the storage device.

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