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    23.
    发明专利
    未知

    公开(公告)号：DE69827601D1

    公开(公告)日：2004-12-23

    申请号：DE69827601

    申请日：1998-03-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MALOBERTI FRANCO ,  ONETO ANDREA ,  TORELLI GUIDO

    IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C16/26 ,  G11C11/00

    Abstract: Method (200) for reading a multiple-level memory cell (C12) capable of taking on three or more states which are represented by different values of a physical quantity (Icell) and each of which is associated with a corresponding logical value (LVcell), comprising the steps of setting (210) an actual physical quantity (Is1) to a value correlated with the value of the physical quantity (Icell) corresponding to the state of the memory cell (C12), and repeating (235), up to the complete determination of the logical value (LVcell) corresponding to the state of the memory cell (C12), a cycle (215-235) comprising the steps of setting (227, 232) a component of the logical value (Di) to a value which is a function of a range in which the actual physical quantity (Isi) lies, determined by comparing (215, 220) the actual physical quantity (Isi) with at least one reference physical quantity (Iri) having a predetermined value lying between a minimum value and a maximum value for the actual physical quantity (Isi), and setting (237) the actual physical quantity for a possible next cycle (Is(i+1)) to a relative value of the actual physical quantity (Isi) with respect to the range in which it lies.

    24.
    发明专利
    未知

    公开(公告)号：IT1318892B1

    公开(公告)日：2003-09-19

    申请号：ITMI20002018

    申请日：2000-09-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  MANSTRETTA ALESSANDRO ,  TORELLI GUIDO

    IPC: G11C7/06 ,  G11C16/28

    Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, at least one differential amplifier connected at the input of the first and the second nodes and having an output terminal to provide a logic signal correlated to the selected cell information, a first voltage-controlled discharge switch circuit connected to the first node and to a voltage reference, a second switch circuit connected to the second node and the voltage reference, and first and second voltage comparator circuits receiving the first selected cell voltage and the second reference cell voltage.

    25.
    发明专利
    未知

    公开(公告)号：DE69901259T2

    公开(公告)日：2002-12-05

    申请号：DE69901259

    申请日：1999-06-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MANSTRETTA ALESSANDRO ,  PIERIN ANDREA ,  TORELLI GUIDO

    IPC: G11C16/06 ,  G11C5/14

    Abstract: A monolithically integrated selector for electrically programmable memory cell devices can be switched at an output terminal (OUT) between a high voltage (HV) and a low voltage (LV). It comprises a leg (N2, N1) of fast ground discharge (GND) from the output terminal, a discharge control leg (P1, N3, N4) driving the selector switching through a phase generator (PHG).

    28.
    发明专利
    未知

    公开(公告)号：ITMI20002018A1

    公开(公告)日：2002-03-15

    申请号：ITMI20002018

    申请日：2000-09-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  TORELLI GUIDO ,  MANSTRETTA ALESSANDRO

    IPC: G11C7/06 ,  G11C16/28

    Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, at least one differential amplifier connected at the input of the first and the second nodes and having an output terminal to provide a logic signal correlated to the selected cell information, a first voltage-controlled discharge switch circuit connected to the first node and to a voltage reference, a second switch circuit connected to the second node and the voltage reference, and first and second voltage comparator circuits receiving the first selected cell voltage and the second reference cell voltage.

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