公开(公告)号：ITMI20000469A1

公开(公告)日：2001-09-10

申请号：ITMI20000469

申请日：2000-03-09

Applicant: ST MICROELECTRONICS SRL

Inventor： BRUCCOLERI MELCHIORRE ,  PISATI VALERIO ,  DEMICHELI MARCO

IPC: G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  H03F3/45

公开(公告)号：DE69427471D1

公开(公告)日：2001-07-19

申请号：DE69427471

申请日：1994-07-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  ALINI ROBERTO ,  CASTELLO RINALDO ,  VAI GIANFRANCO

IPC: H03F3/343 ,  H03F3/45 ,  H03G1/00 ,  H03H11/24 ,  H03F1/08 ,  H03H11/04

公开(公告)号：DE69520562T2

公开(公告)日：2001-07-12

申请号：DE69520562

申请日：1995-05-15

Applicant: ST MICROELECTRONICS SRL

Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE ,  PISATI VALERIO

IPC: H03M1/68 ,  G06J1/00 ,  H03M1/66 ,  H03M1/78 ,  H03M1/00

Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

公开(公告)号：ITMI20000393D0

公开(公告)日：2000-02-29

申请号：ITMI20000393

申请日：2000-02-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTELLO RINALDO ,  PORTALURI SALVATORE ,  PISATI VALERIO ,  CAZZANIGA MARCO

IPC: H03F1/42 ,  H03H11/04

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.

公开(公告)号：DE69825558D1

公开(公告)日：2004-09-16

申请号：DE69825558

申请日：1998-03-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PORTALURI SALVATORE ,  PISATI VALERIO ,  ZANGRANDI LUIGI

IPC: H03K7/08

Abstract: A device for generating pulses of high-precision programmable duration, whose particularity is the fact that it comprises: -- first pulse generator means (1) which are suitable to receive in input a pulse generation command signal (IN) and to emit in output a first pulse for loading the contents of a register in counter means (2); -- second pulse generator means (4), triggered by the first pulse in output from the first pulse generator means (1); -- third pulse generator means (6), triggered by a second pulse emitted by the second pulse generator means and suitable to generate a third pulse to restart the second pulse generator means; the second pulse emitted by the second pulse generator means (4) constituting a clock signal for the counter means (2) in order to produce a decrement in the counter means; the signal in output from the counter means (2) being the pulsed signal to be generated (OUT); the duration of the pulsed signal being determined by the content of the counter means (2).

公开(公告)号：DE69824143D1

公开(公告)日：2004-07-01

申请号：DE69824143

申请日：1998-03-31

Applicant: ST MICROELECTRONICS SRL

Inventor： MARCHESE STEFANO ,  PISATI VALERIO ,  PORTALURI SALVATORE ,  SAVO ALESSANDRO

IPC: H03G1/00 ,  H03G7/06 ,  H03G3/00 ,  H03G7/00

Abstract: An amplifier with programmable gain and input linearity, comprising an input stage (10), which is suitable to receive a voltage signal (V , V ) and perform current conversion thereof with compression, and an output stage (30), which is connected to the input stage (10) and is suitable to decompress the signal in output from the input stage, producing gain amplification thereof; the particularity of the amplifier is the fact that it further comprises at least one current amplifier stage (20) which is interposed between the input stage (10) and the output stage (30) and comprises at least one bipolar transistor (21, 22) which is series-connected to a load diode (23, 24) and to a current source (2I2); programmable means (I2, I2*) for reducing the transconductance of the load diode (23, 24) being provided in the at least one amplifier stage (20) to determine a programmable amplification factor for the gain of the amplifier.

公开(公告)号：DE69529397D1

公开(公告)日：2003-02-20

申请号：DE69529397

申请日：1995-02-22

Applicant: ST MICROELECTRONICS SRL

Inventor： ALINI ROBERTO ,  BRIANTI FRANCESCO ,  PISATI VALERIO ,  DEMICHELI MARCO

IPC: H03H11/04 ,  H03H15/00 ,  H03H17/00 ,  H03M13/23 ,  H03H1/00

公开(公告)号：DE69520562D1

公开(公告)日：2001-05-10

申请号：DE69520562

申请日：1995-05-15

Applicant: ST MICROELECTRONICS SRL

Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE ,  PISATI VALERIO

IPC: H03M1/68 ,  G06J1/00 ,  H03M1/66 ,  H03M1/78 ,  H03M1/00

Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

公开(公告)号：ITMI990350A1

公开(公告)日：2000-08-21

申请号：ITMI990350

申请日：1999-02-19

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  PORTALURI SALVATORE ,  MARCHESE STEFANO ,  SAVO ALESSANDRO

IPC: H03G1/00

公开(公告)号：DE69421072T2

公开(公告)日：2000-04-20

申请号：DE69421072

申请日：1994-05-23

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  PISATI VALERIO

IPC: G11B20/14 ,  G11B5/02 ,  G11B5/09 ,  G11B5/596 ,  G11B20/06 ,  G11B20/10 ,  G11B20/18 ,  G11B21/10

Abstract: The device is to be used with a parallel architecture PRML reading apparatus comprising a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel processing channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two processing channels (24, 34) comprise respective analog-digital converters (26, 36) and respective Viterbi detectors (27, 37) and operate according to sampling sequences that alternate with one another. The device (30) for processing the servo signals comprises a rectifier (31) connected to the outputs of said analog-digital converters (26, 36) and an integrator (32).