公开(公告)号：EP0978844B1

公开(公告)日：2005-11-02

申请号：EP98830491.1

申请日：1998-08-07

Applicant: STMicroelectronics S.r.l.

Inventor： Calligaro, Cristiano ,  Rolandi, Paolo ,  Gastaldi, Roberto ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C2211/5634

公开(公告)号：EP1548744A1

公开(公告)日：2005-06-29

申请号：EP03425820.2

申请日：2003-12-23

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Torelli, Guido

IPC: G11C11/34 ,  G11C8/10

CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004

Abstract: A memory device includes a plurality of memory cells (3), arranged in row and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (V A ); a column addressing circuit (4) for addressing a bit line (12) corresponding to a memory cell (3) to be read; and a row addressing circuit (5) for addressing a word line (13) corresponding to the memory cell (3) to be read. Moreover, the column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the memory cell (3) to be read substantially at the supply voltage (V A ).

Abstract translation: 一种存储器装置包括布置在具有连接到相同的位线（12）和存储单元respectivement第一端子（3a）中同一列的存储单元的多个（3），以行和列排列的存储器单元（3）（3 ）布置在具有respectivement第二端子在同一行（3B）选择性地连接到一个相同的字线（13）; 一电源线（9）提供电源电压（VA）; 用于寻址对应于存储单元（3）要被读出的位线（12）的柱寻址电路（4）; 和要被读取用于寻址对应于存储单元（3）的字线（13）的行寻址电路（5）。 更完了，列寻址电路（4）被配置成偏置相应于存储单元（3）被寻址的位线（12）被在电源电压（VA）基本上读取。

公开(公告)号：EP0833340B1

公开(公告)日：2003-04-02

申请号：EP96830494.9

申请日：1996-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Calligaro, Cristiano ,  Rolandi, Paolo ,  Gastaldi, Roberto ,  Torelli, Guido

IPC: G11C7/00 ,  G11C11/56

CPC classification number: G11C7/062 ,  G11C7/06 ,  G11C7/065 ,  G11C11/5621 ,  G11C11/5642

公开(公告)号：EP0811986B1

公开(公告)日：2003-03-12

申请号：EP96830318.0

申请日：1996-06-05

Applicant: STMicroelectronics S.r.l.

Inventor： Calligaro, Cristiano ,  Gastaldi, Roberto ,  Manstretta, Alessandro ,  Cappelletti, Paolo ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632 ,  G11C2211/5634

公开(公告)号：EP1249842A1

公开(公告)日：2002-10-16

申请号：EP01830247.1

申请日：2001-04-10

Applicant: STMicroelectronics S.r.l.

Inventor： Gregori, Stefano ,  Micheloni, Rino ,  Pierin, Andrea ,  Khouri, Osama ,  Torelli, Guido

IPC: G11C16/12

CPC classification number: G11C11/5628 ,  G11C16/12

Abstract: Described herein is a method for programming a nonvolatile memory cell (1), which envisages applying in succession, to the gate terminal (2) of the memory cell (1), at least a first and a second programming pulse trains (F1, F2) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train (F1) is greater than the amplitude increment between one pulse and the next in the second programming pulse train (F2). Advantageously, the programming method envisages applying, to the gate terminal (2) of the memory cell (1) and before the first programming pulse train (F1), also a third programming pulse train (F0; F3) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train (F1) and substantially equal to the amplitude increment in the second programming pulse train (F2), or else may be greater than the amplitude increment in the first programming pulse train (F1).

Abstract translation: 该方法涉及将相继地向存储单元的控制端子，至少两个编程脉冲串（F1，F2）与脉冲幅度在楼梯方式增加。 一个脉冲，并在第一编程脉冲串（F1）的下一个之间的幅度增量比一个脉冲，并在第二编程脉冲串（F2）的下一个之间的幅度增量越大。 从所述第一编程脉冲来训练到第二转换时当存储器单元具有与一个参考值的预先设定的关系的阈值电压。

公开(公告)号：EP0961288A1

公开(公告)日：1999-12-01

申请号：EP98830332.7

申请日：1998-05-29

Applicant: STMicroelectronics S.r.l.

Inventor： Manstretta, Alessandro ,  Pierin, Andrea ,  Torelli, Guido

IPC: G11C16/06

CPC classification number: G11C16/12

Abstract: A selector switch monolithically integrated to a CMOS technology circuit for electrically programmable memory cell devices having at least first and second input terminals for coupling to first and second voltage generators (HV and LV), respectively, and an output terminal (OUT).
First (P1) and second (P2) field-effect selection transistors are respectively connected, via first and second terminals, between the first input terminal and the output terminal and between the second input terminal and the output terminal. These transistors are driven through control terminals at non-overlapping phases and have body terminals connected at a body circuit node (BODY) which is coupled to the first and second voltage generators through a bias circuit block (WBC) effective to bias the node to the higher of the instant voltages generated by the first and second generators.

Abstract translation: 选择器开关单片集成到用于电可编程存储器单元器件的CMOS工艺电路，其具有至少分别用于耦合到第一和第二电压发生器（HV和LV）的第一和第二输入端子以及输出端子（OUT）。 第一（P1）和第二（P2）场效应选择晶体管分别经由第一和第二端子在第一输入端和输出端之间以及第二输入端和输出端之间连接。 这些晶体管以不重叠的相位被驱动通过控制端子，并且具有连接在体电路节点（BODY）的主体端子，其通过偏置电路块（WBC）耦合到第一和第二电压发生器，该偏置电路块有效地将节点偏置到 由第一和第二发生器产生的瞬时电压越高。

公开(公告)号：EP0862270A1

公开(公告)日：1998-09-02

申请号：EP97830084.6

申请日：1997-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele, Vincenzo ,  Manstretta, Alessandro ,  Rolandi, Paolo ,  Torelli, Guido

IPC: H03K4/02 ,  G05F1/46

CPC classification number: G05F1/465 ,  H03K4/023

Abstract: A stair-case adaptive voltage generator circuit, which circuit comprises a first capacitor (CB) connected between a first voltage reference (Vref) and an output operational amplifier (CA), through first (T1 and second (T4) switches, respectively.
The terminals of the capacitor are also connected to a second voltage reference (Vinit) through third (T3) and fourth (T2) switches, respectively.
A second capacitor (CA), in series with a fifth switch (CNT), is connected in parallel to the first capacitor (CB).

Abstract translation: 一个阶梯式自适应电压发生器电路，该电路包括分别通过第一（T1和第二（T4）开关连接在第一电压基准（Vref）和输出运算放大器（CA）之间的第一电容器（CB）。 电容器的端子也分别通过第三（T3）和第四（T2）开关连接到第二参考电压（Vinit），与第五开关（CNT）串联的第二电容器（CA）并联 到第一个电容（CB）

公开(公告)号：EP1211812A2

公开(公告)日：2002-06-05

申请号：EP00127649.2

申请日：2000-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Khouri, Osama ,  Pierin, Andrea ,  Gregori, Stefano ,  Torelli, Guido

IPC: H03M1/14

CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

Abstract: The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg).
The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB).
The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.

Abstract translation: 本发明涉及到模拟 - 数字转换方法和相关的设备，在高密度的多级非易失性存储器装置。 该方法适用于多级存储器单元包括具有漏极和源极端子的浮栅晶体管; 要读出的单元是通过，施加预定的偏置电压值到它的漏极和源极端，而其漏极端子施加规定的电流值（Iref的）经受读取操作，并通过测量其栅极电压的值（Vg的 ）。 本发明的方法包括包含在所述存储器单元中的最显著位（MSB）的第一转化阶段，接着是至少显著位的第二阶段的转换（LSB）。 第一个步骤是一个时间间隙（T1-T0），其对应于栅极电压信号（VG）的上升瞬变内完成，而第二个步骤是在瞬变结束启动。

公开(公告)号：EP0724266B1

公开(公告)日：2001-12-12

申请号：EP95830023.8

申请日：1995-01-27

Applicant: STMicroelectronics S.r.l.

Inventor： Calligaro, Cristiano ,  Daniele, Vincenzo ,  Gastaldi, Roberto ,  Manstretta, Alessandro ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632

公开(公告)号：EP1074995A1

公开(公告)日：2001-02-07

申请号：EP99830501.5

申请日：1999-08-03

Applicant: STMicroelectronics S.r.l.

Inventor： Torelli, Guido ,  Modelli, Alberto ,  Manstretta, Alessandro

IPC: G11C11/56

CPC classification number: G11C11/5621 ,  G11C11/5628

Abstract: When programming, for each programming pulse, a threshold voltage whose value is increased with respect to the previous programming pulse is applied to the gate terminal of each cell to be programmed. After an initial step, the increase of threshold voltage of the cell being programmed becomes equal to the applied gate voltage increase (ΔV GP ). In order to reduce the global programming time, keeping a small variability interval of threshold voltages associated with each level, to pass from a threshold level to a following one, each cell to be programmed is supplied with a plurality of consecutive pulses without verify (107-109), until it immediately goes below the voltage level to be programmed, and then a verify step (110) is performed, followed by subsequent programming and verify steps (112, 110, 117, 118) until the cell to be programmed reaches the desired threshold value.

Abstract translation: 当编程时，对于每个编程脉冲，其值相对于先前编程脉冲增加的阈值电压被施加到要编程的每个单元的栅极端子。 在初始步骤之后，被编程的单元的阈值电压的增加等于施加的栅极电压增加（DELTA VGP）。 为了减少全局编程时间，保持与每个电平相关联的阈值电压的小变化间隔从阈值电平传递到随后的每个要编程的每个单元被提供多个连续的脉冲而不验证（107 -109），直到其立即低于要编程的电压电平，然后执行验证步骤（110），随后进行后续编程和验证步骤（112,110,117,118），直到待编程的单元达到 所需的阈值。