公开(公告)号：US20170144881A1

公开(公告)日：2017-05-25

申请号：US15191160

申请日：2016-06-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Lorenzo Baldo ,  Enri Duqi ,  Flavio Francesco Villa

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0045 ,  B81B3/0072 ,  B81B2201/0228 ,  B81B2201/025 ,  B81B2203/0127 ,  B81B2203/0163 ,  B81B2203/0315 ,  B81B2207/012 ,  B81C1/00182 ,  B81C1/00325 ,  B81C2201/0116 ,  B81C2201/0173 ,  B81C2203/0785 ,  G02B26/0858

Abstract: A micro-electro-mechanical device formed in a monolithic body of semiconductor material accommodating a first buried cavity; a sensitive region above the first buried cavity; and a second buried cavity extending in the sensitive region. A decoupling trench extends from a first face of the monolithic body as far as the first buried cavity and laterally surrounds the second buried cavity. The decoupling trench separates the sensitive region from a peripheral portion of the monolithic body.

公开(公告)号：US20150340268A1

公开(公告)日：2015-11-26

申请号：US14819520

申请日：2015-08-06

Applicant: Infineon Technologies Dresden GMBH

Inventor： Thoralf Kautzsch ,  Alessia Scire ,  Steffen Bieselt

IPC: H01L21/764 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L21/764 ,  B81B2203/0315 ,  B81C1/00047 ,  B81C2201/0116 ,  H01L21/3247 ,  H01L21/7624 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7833

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The first cavity is disposed under a portion of the substrate. The method further includes forming a first pillar within the first cavity to support the portion of the substrate.

Abstract translation: 根据本发明的实施例，形成半导体器件的方法包括在衬底内形成第一空腔。 第一空腔设置在基板的一部分下方。 该方法还包括在第一腔内形成第一支柱以支撑衬底的该部分。

公开(公告)号：US08735286B2

公开(公告)日：2014-05-27

申请号：US13284431

申请日：2011-10-28

Applicant: Rishi Kant ,  Roger Thomas Howe

Inventor： Rishi Kant ,  Roger Thomas Howe

IPC: H01L21/44

CPC classification number: B81C1/00333 ,  B81C2201/0116

Abstract: A method for sealing through-holes in a material via material diffusion, without the deposition of a sealant material, is disclosed. The method is well suited to the fabrication and packaging of microsystems technology-based devices and systems. In some embodiments, the method comprises forming sacrificial material release through-holes through a structural layer, removing the sacrificial material via an etch that etches the sacrificial material through the release through-holes, and sealing of the release through-holes via material diffusion.

Abstract translation: 公开了一种用于通过材料扩散密封材料中的通孔的方法，而不会密封材料的沉积。 该方法非常适合基于微系统技术的设备和系统的制造和封装。 在一些实施例中，该方法包括通过结构层形成牺牲材料释放通孔，通过经由释放通孔蚀刻牺牲材料的蚀刻以及经由材料扩散密封释放通孔来去除牺牲材料。

公开(公告)号：US20130221495A1

公开(公告)日：2013-08-29

申请号：US13721496

申请日：2012-12-20

Applicant: The Hong Kong University of Science and Technology

Inventor： Man WONG ,  Fan ZENG

IPC: H01L21/461 ,  H01L29/16

CPC classification number: H01L21/461 ,  B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00822 ,  B01J2219/00828 ,  B01J2219/00837 ,  B01J2219/0086 ,  B01L3/502707 ,  B01L2300/0816 ,  B81B2201/058 ,  B81B2203/0338 ,  B81C1/00071 ,  B81C2201/0116 ,  B81C2201/0178 ,  H01L29/16

Abstract: Described herein is a microchannel that is formed beneath and parallel to a surface of a silicon substrate. Silicon migration technology is utilized to form a microchannel that is buried beneath the surface of the silicon substrate. Etching opens at least one end of the microchannel. Oxidization is utilized through the open end of the microchannel to facilitate a controlled diameter of the microchannel.

Abstract translation: 这里描述的是形成在硅衬底的表面下方并平行于其的表面的微通道。 利用硅迁移技术形成埋在硅衬底表面下方的微通道。 蚀刻打开微通道的至少一端。 通过微通道的开口端利用氧化，以促进微通道的受控直径。

公开(公告)号：US20050181529A1

公开(公告)日：2005-08-18

申请号：US11011888

申请日：2004-12-13

Applicant: Hubert Benzel ,  Frank Schaefer ,  Simon Armbruster ,  Gerhard Lammel ,  Christoph Schelling ,  Joerg Brasas

Inventor： Hubert Benzel ,  Frank Schaefer ,  Simon Armbruster ,  Gerhard Lammel ,  Christoph Schelling ,  Joerg Brasas

IPC: B81B3/00 ,  H01L21/00 ,  H01L29/24 ,  H01L33/00

CPC classification number: B81C1/00158 ,  B81B3/007 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0116 ,  B81C2201/0136

Abstract: A manufacturing method for a micromechanical semiconductor element includes providing on a semiconductor substrate a patterned stabilizing element having at least one opening. The opening is arranged such that it allows access to a first region in the semiconductor substrate, the first region having a first doping. Furthermore, a selective removal of at least a portion of the semiconductor material having the first doping out of the first region of the semiconductor substrate is provided. In addition, a membrane is produced above the first region using a first epitaxy layer applied on the stabilizing element. In a further method step, at least a portion of the first region is used to produce a cavity underneath the stabilizing element. In this manner, the present invention provides for the production of the patterned stabilizing element by means of a second epitaxy layer, which is applied on the semiconductor substrate.

Abstract translation: 微机电半导体元件的制造方法包括在半导体衬底上提供具有至少一个开口的图案化稳定元件。 开口被布置成使得其允许接近半导体衬底中的第一区域，第一区域具有第一掺杂。 此外，提供了选择性地去除半导体衬底的第一区域中具有第一掺杂的半导体材料的至少一部分。 此外，使用施加在稳定元件上的第一外延层，在第一区域上方产生膜。 在另一方法步骤中，第一区域的至少一部分用于在稳定元件下方产生空腔。 以这种方式，本发明提供了通过施加在半导体衬底上的第二外延层来生产图案化的稳定元件。

公开(公告)号：EP1967488A3

公开(公告)日：2008-09-17

申请号：EP08104525.4

申请日：2004-11-02

Applicant: ROBERT BOSCH GMBH

Inventor： Lammel, Gerhard ,  Benzel, Hubert ,  Schaefer, Frank ,  Armbruster, Simon ,  Schelling, Christoph ,  Brasas, Joerg

IPC: B81B3/00

CPC classification number: B81B3/007 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00658 ,  B81C2201/0115 ,  B81C2201/0116 ,  B81C2201/0136

Abstract: Die Erfindung beschreibt ein Verfahren zur Herstellung eines Halbleiterbauelements, insbesondere eines mikromechanischen Membransensors, sowie ein Halbleiterbauelement nach einem der beanspruchten Herstellungsverfahren, mit einem Halbleiterträger, einer Membran und einer Kaverne.

公开(公告)号：EP1544163A3

公开(公告)日：2006-07-05

申请号：EP04105448.7

申请日：2004-11-02

Applicant: ROBERT BOSCH GMBH

Inventor： BENZEL, Hubert ,  SCHAEFER, Frank ,  ARMBRUSTER, Simon ,  Lammel, Gerhard ,  SCHELLING, Christoph ,  BRASAS, Joerg

IPC: B81B3/00

CPC classification number: B81C1/00158 ,  B81B3/007 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0116 ,  B81C2201/0136

Abstract: Die Anmeldung beschreibt ein Herstellungsverfahren eines insbesondere mikromechanischen Halbleiterbauelements sowie ein mit diesem Verfahren hergestelltes Halbleiterbauelement. Zur Herstellung des Halbleiterbauelements ist vorgesehen, dass auf einem Halbleiterträger ein strukturiertes Stabilisierungselement mit wenigstens einer Öffnung erzeugt wird. Die Öffnung ist dabei so angebracht, dass sie den Zugang zu einem mit einer ersten Dotierung aufweisenden ersten Bereich im Halbleiterträger erlaubt. Weiterhin ist ein selektives Herauslösen wenigstens eines Teils des mit der ersten Dotierung versehenen Halbleitermaterials aus dem ersten Bereich des Halbleiterträger vorgesehen. Darüber hinaus wird mittels einer ersten Epitaxieschicht, die auf das Stabilisierungselement aufgebracht wird, eine Membran oberhalb des ersten Bereichs erzeugt. Wenigstens ein Teil des ersten Bereichs dient in einem weiteren Verfahrensschritt dazu, eine Kaverne unterhalb des Stabilisierungselement zu erzeugen. Der Kern der Anmeldung besteht nun darin, das strukturierte Stabilisierungselement mittels einer zweiten Epitaxieschicht, die auf dem Halbleiterträger aufgebracht wird, zu erzeugen.

公开(公告)号：EP1427010A1

公开(公告)日：2004-06-09

申请号：EP02425742.0

申请日：2002-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Renna, Crocifisso Marco Antonio ,  La Magna, Luigi ,  Lorenti, Simona ,  Coffa, Salvatore

IPC: H01L21/764 ,  H01L21/3063 ,  H01L21/762 ,  H01L29/06 ,  B81B1/00 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

Abstract: A method for manufacturing a semiconductor substrate (7) of a first concentration type is described, which comprises at least a buried insulating cavity (10b, 10d), comprising the following steps:

form on the semiconductor substrate (7) a plurality of trenches (8, 10),
form a surface layer (7a, 9a) on the semiconductor substrate in order to close superficially the plurality of trenches (8, 10) forming in the meantime at least a buried cavity (10b) in correspondence with the surface-distal end of the trenches (8, 10).

Devices manufactured with the method according to the invention are also described.

Abstract translation: 一种用于制造（7）的第一浓度类型的，描述了一种半导体衬底的方法，其包括至少一个掩埋绝缘腔（10B，10D）包括以下步骤：形式在半导体基片（7）的沟槽的多个（ 8，10），形成在半导体衬底的表面层（图7A，图9A）以闭合表面上的沟槽（8的多元性，10）（图10b），其与所述表面对应的平均时间中形成至少一个掩埋空腔 沟槽（8，10）的远端。 因此与方法雅丁本发明制造设备进行了描述。

公开(公告)号：EP1427010B1

公开(公告)日：2012-01-11

申请号：EP02425742.0

申请日：2002-11-29

Applicant: STMicroelectronics Srl

Inventor： Renna, Crocifisso Marco Antonio ,  La Magna, Luigi ,  Lorenti, Simona ,  Coffa, Salvatore

IPC: H01L21/764 ,  H01L21/3063 ,  H01L21/762 ,  H01L29/06 ,  B81B1/00 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

公开(公告)号：EP2280412A3

公开(公告)日：2011-02-16

申请号：EP10184095.7

申请日：2002-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Renna, Crocifisso Marco Antonio ,  La Magna, Luigi ,  Lorenti, Simona ,  Coffa, Salvatore

IPC: H01L21/764 ,  H01L21/3063 ,  H01L21/762 ,  H01L29/06 ,  B81C1/00 ,  H01L21/302 ,  H01L21/306

CPC classification number: B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

Abstract: A semiconductor substrate comprising at least a buried insulating cavity (10b, 10d) and comprising:
- a semiconductor substrate (7) having a first type of concentration and having a plurality of trenches (8, 10),
- a surface layer (7a, 9a) on said semiconductor substrate (7) in order to close superficially said plurality of trenches (8, 10) forming said at least a buried insulating cavity (10b, 10d);
- a first semiconductor material layer (9) on said surface layer (7a, 9a) having the same first type of concentration as said semiconductor substrate (7), said first semiconductor material layer (9) comprising at least a trench (11) which is in communication with said at least a buried insulating cavity (10b, 10d).