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公开(公告)号：KR101794017B1
公开(公告)日：2017-11-06
申请号：KR1020110044612
申请日：2011-05-12
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/04 , H01L27/249 , H01L45/12 , H01L45/1226 , H01L45/146
Abstract: 저항메모리장치및 그제조방법이제공된다. 상기저항메모리장치는저항메모리장치의일 태양(aspect)은서로이격되고순차적으로적층된제1 층간절연막및 제2 층간절연막, 상기제1 층간절연막및 상기제2 층간절연막을관통하도록형성된제1 전극, 상기제1 층간절연막의상면, 상기제1 전극의측면및 상기제2 층간절연막의하면을따라형성된저항변화막, 및상기제1 층간절연막및 제2 층간절연막사이에형성된제2 전극을포함한다.
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公开(公告)号：KR101692446B1
公开(公告)日：2017-01-04
申请号：KR1020100064413
申请日：2010-07-05
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11582 , H01L27/1157
Abstract: 3차원반도체장치및 그제조방법이제공된다. 이장치는차례로적층된도전패턴들을포함하면서기판상에배치되는도전구조체, 도전구조체를관통하여기판의상부면에삽입되는반도체패턴, 및상기반도체패턴과상기도전구조체사이에개재되는절연막구조체를포함한다. 또한, 반도체패턴은절연막구조체의아래에서수평적으로연장되어기판의측벽과직접접촉한다.
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公开(公告)号：KR1020160144164A
公开(公告)日：2016-12-16
申请号：KR1020150080591
申请日：2015-06-08
Applicant: 삼성전자주식회사
CPC classification number: H01L29/4991 , H01L21/7682 , H01L21/76897 , H01L21/823431 , H01L21/823481 , H01L23/485 , H01L27/0886 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/7848
Abstract: 반도체소자및 그의형성방법이제공된다. 상기반도체소자는소자분리막상에위치하는게이트어셈블리; 상기게이트어셈블리의측면상에위치하는게이트스페이서; 상기게이트스페이서상에위치하는컨택어셈블리; 상기소자분리막과상기컨택어셈블리사이에위치하는에어갭; 및상기게이트스페이서와상기에어갭 사이에위치하는제 1 스페이서캡핑막을포함한다. 상기제 1 스페이서캡핑막은상기게이트스페이서와식각선택비를갖는다.
Abstract translation: 半导体器件包括设置在器件隔离层上的栅极组件，设置在栅极组件的侧表面上的栅极间隔件，设置在栅极间隔物上的接触组件，设置在器件隔离层和接触组件之间的气隙， 以及设置在所述栅极间隔物和所述气隙之间的第一间隔物封盖层。 第一间隔物覆盖层相对于栅极间隔物具有蚀刻选择性。
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公开(公告)号：KR1020140012419A
公开(公告)日：2014-02-03
申请号：KR1020120079269
申请日：2012-07-20
Applicant: 삼성전자주식회사
CPC classification number: H01L43/02 , G11C11/1659 , H01L43/08 , H01L43/12
Abstract: A magnetic memory device and a method for manufacturing the same are provided. The magnetic memory device includes a magnetic tunnel junction having a lower magnetic structure, an upper magnetic structure, and a tunnel barrier therebetween, wherein the tunnel barrier may have a wider width than that of the lower magnetic structure.
Abstract translation: 提供一种磁存储器件及其制造方法。 磁存储器件包括具有较低磁性结构的磁性隧道结，上部磁性结构和它们之间的隧道屏障，其中隧道势垒可以具有比下部磁性结构宽的宽度。
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Patent Agency Ranking
公开(公告)号：KR1020130091153A
公开(公告)日：2013-08-16
申请号：KR1020120012463
申请日：2012-02-07
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/2463 , G11C16/0483 , H01L27/10882 , H01L27/2436
Abstract: PURPOSE: A semiconductor memory device and a forming method thereof are provided to improve integration by arranging a semiconductor pattern between a first segment and a second segment. CONSTITUTION: A first segment includes a first memory element (150). The first memory element is interposed between first horizontal electrodes and first vertical electrodes. A second segment includes a second memory element (155). The second memory element is interposed between second horizontal electrodes and second vertical electrodes. A first semiconductor pattern (170) is arranged between the first and second segments.
Abstract translation: 目的：提供半导体存储器件及其形成方法，以通过在第一段和第二段之间布置半导体图案来改善集成。 构成：第一段包括第一存储元件（150）。 第一存储元件介于第一水平电极和第一垂直电极之间。 第二段包括第二存储元件（155）。 第二存储元件介于第二水平电极和第二垂直电极之间。 第一半导体图案（170）布置在第一和第二段之间。
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公开(公告)号：KR1020130004784A
公开(公告)日：2013-01-14
申请号：KR1020110066052
申请日：2011-07-04
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L2924/0002 , H01L21/823487 , H01L2924/00
Abstract: PURPOSE: A non-volatility memory device had and a manufacturing method thereof are provided to form a buffer layer between a bit pillar and a molding layer and to prevent the etch damage of the bit pillar and the resistance changeable element. CONSTITUTION: A substrate buffer film(19) is formed on a semiconductor substrate(11). A first molding film(21) is formed on the substrate buffer film. A horizontal line(61) is formed on the first molding film. A second molding film(22) is formed on the horizontal line. A bit pillar which perpendicularly passes through the molding film and the horizontal line is formed. A resistance changeable element(44) and a diode film(57) are formed between the bit pillar and the horizontal line.
Abstract translation: 目的：提供非挥发性记忆装置及其制造方法，以在位柱和成型层之间形成缓冲层，并防止位柱和电阻可变元件的蚀刻损伤。 构成：在半导体衬底（11）上形成衬底缓冲膜（19）。 在基板缓冲膜上形成第一成型膜（21）。 在第一成型膜上形成水平线（61）。 在水平线上形成第二成型膜（22）。 形成垂直地穿过成型膜和水平线的位柱。 在位柱和水平线之间形成电阻可变元件（44）和二极管膜（57）。
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公开(公告)号：KR1020090062613A
公开(公告)日：2009-06-17
申请号：KR1020070129965
申请日：2007-12-13
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/792 , H01L21/28282 , H01L29/4234 , H01L29/517 , H01L29/66833
Abstract: A nonvolatile memory device and a method for manufacturing the same are provided to obtain uniform distribution by using a silicon nitride film including the metal as a charge trap layer. A gate structure(20) is formed on a semiconductor substrate(10). The gate structure is comprised of a tunnel dielectric layer, a charge trap layer, a blocking dielectric layer and a gate electrode. A source/drain region(12) is formed within the semiconductor substrate of both sides of the gate structure. The charge trap layer is comprised of the nitride film including the metal. The metal is selected among the transition metal. The rate of the transition metal is within the range of 1 to 50% not to lose a nonconductor characteristic of the nitride film. The charge trap layer is made of a titanium silicon nitride film or the tantalum silicon nitride film.
Abstract translation: 提供一种非易失性存储器件及其制造方法，以通过使用包含该金属的氮化硅膜作为电荷陷阱层来获得均匀的分布。 在半导体衬底（10）上形成栅极结构（20）。 栅极结构由隧道介电层，电荷陷阱层，阻挡电介质层和栅电极构成。 源极/漏极区域（12）形成在栅极结构的两侧的半导体衬底内。 电荷陷阱层由包括金属的氮化物膜构成。 在过渡金属中选择金属。 过渡金属的比例在1〜50％的范围内，不会损失氮化膜的非导体特性。 电荷陷阱层由氮化硅钛膜或氮化钽膜制成。
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公开(公告)号：KR100855990B1
公开(公告)日：2008-09-02
申请号：KR1020070030047
申请日：2007-03-27
Applicant: 삼성전자주식회사 , 리전츠 오브 더 유니버시티 오브 캘리포니아
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/115 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/0688 , H01L27/11517 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L21/76224
Abstract: A non-volatile memory device and a manufacturing method thereof are provided to increase integration degree by forming a stack structure instead of a plane structure. A plurality of semiconductor layers(120) are laminated on a substrate(105). A plurality of second semiconductor layers(115) are inserted between the first semiconductor layers. The second semiconductor layers are recessed from one end of the first semiconductor layers in order to define a plurality of first trenches. A plurality of first storage nodes(140a) are formed on surfaces of the second semiconductor layers in the first trenches. A plurality of first control gate electrodes(150a) are formed on the first storage nodes in order to fill up the first trenches.
Abstract translation: 提供非易失性存储器件及其制造方法，以通过形成堆叠结构而不是平面结构来提高积分度。 多个半导体层（120）层叠在基板（105）上。 多个第二半导体层（115）插入在第一半导体层之间。 第二半导体层从第一半导体层的一端凹入以限定多个第一沟槽。 多个第一存储节点（140a）形成在第一沟槽中的第二半导体层的表面上。 在第一存储节点上形成多个第一控制栅电极（150a），以便填充第一沟槽。
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公开(公告)号：KR1020080051014A
公开(公告)日：2008-06-10
申请号：KR1020070095665
申请日：2007-09-20
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/2463 , H01L27/2436 , H01L27/2481
Abstract: An AND-type and NOR-type flash memory arrays, a manufacturing method thereof and an operating method thereof are provided to form plural same silicon pins having certain width and height on an upper portion of a substrate. A local bit line(LBL1) is connected to bit lines(BL1,BL2,BLn) via a first select transistor(ST11). Memory cells(M11 to Mm1) are connected in parallel to the local bit line and the local source line. A local source line(LSL1) is commonly connected to a source of the respective memory cells, and a common source line(CSL) is connected to the local source line via a second select transistor(ST21). A drain select line(DSL) and a source select line(SSL) are electrically connected to a gate of the first select transistor and a gate of the second select transistor. Plural word lines(WL1 to WLm) are connected to a gate of each memory cell. The local bit line and the local source line have a first doped layer and a second doped layer which are vertically spaced apart from silicon pins.
Abstract translation: 提供AND型和NOR型闪速存储器阵列，其制造方法和操作方法，以在衬底的上部上形成具有一定宽度和高度的多个相同的硅销。 局部位线（LBL1）经由第一选择晶体管（ST11）连接到位线（BL1，BL2，BLn）。 存储单元（M11〜Mm1）与本地位线和本地源极线并联连接。 本地源极线（LSL1）通常连接到各个存储单元的源极，并且公共源极线（CSL）经由第二选择晶体管连接到本地源极线（ST21）。 漏极选择线（DSL）和源选择线（SSL）电连接到第一选择晶体管的栅极和第二选择晶体管的栅极。 多个字线（WL1至WLm）连接到每个存储单元的栅极。 局部位线和局部源极线具有与硅引脚垂直间隔开的第一掺杂层和第二掺杂层。
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