公开(公告)号：SG118102A1

公开(公告)日：2006-01-27

申请号：SG200107602

申请日：2001-12-07

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  ROY ARTHUR CARRUTHERS ,  JAMES MCKELL EDWIN HARPER ,  CHAO-KUN HU ,  KIM YANG LEE ,  ISMAIL CEVDET NOYAN ,  ROBERT ROSENBERG ,  THOMAS MCCARROLL SHAW

IPC: H01L21/28 ,  B32B15/01 ,  C22C27/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/485

Abstract: An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1-XTix, Ta1-X, Hfx, Ta1-X, Inxy, Ta1-XSnx, Ta1-XZrx.

公开(公告)号：BR9404247A

公开(公告)日：1995-06-20

申请号：BR9404247

申请日：1994-10-26

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ALFRED ,  D'HERLE FRANCOIS MAX ,  HARPER JAMES MCKELL EDWING ,  MANN RANDY WILLIAM ,  MILES GLEN LESTER ,  RAKOWSKI DONALD WALTER DOUGLAS

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L23/36

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.

公开(公告)号：CA2118147A1

公开(公告)日：1995-04-30

申请号：CA2118147

申请日：1994-10-14

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE A ,  D HEURLE FRANCOIS M ,  HARPER JAMES M E ,  MANN RANDY W ,  MILES GLEN L ,  RAKOWSKI DONALD W D

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  C30B31/02

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.

公开(公告)号：DE112012003823T5

公开(公告)日：2014-08-07

申请号：DE112012003823

申请日：2012-07-18

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  NOGAMI TAKESHI ,  GAMBINO JEFFREY P ,  HUANG QIANG ,  RODBELL KENNETH P

IPC: H01L21/28

Abstract: Eine Metallverbindungsstruktur und ein Verfahren zur Herstellung der Metallverbindungsstruktur. Mangan (Mn) wird in eine Kupfer(Cu)-Verbindungsstruktur eingebaut, um die Mikrostruktur zu modifizieren, um Bambusstil-Korngrenzen in Sub-90-nm-Technologien zu erreichen. Vorzugsweise sind die Bambuskörner durch Abstände von weniger als der „Blech”-Länge getrennt, so dass eine Kupfer(Cu)-Diffusion durch Korngrenzen vermieden wird. Das hinzugefügte Mn löst auch das Wachstum von Cu-Körnern herunter bis zu der unteren Fläche der Metallleitung aus, so dass eine echte Bambusmikrostruktur gebildet wird, welche bis zu der unteren Fläche reicht, und der Cu-Diffusionsmechanismus entlang Korngrenzen, die entlang der Länge der Metallleitung orientiert sind, eliminiert wird.

公开(公告)号：MY124349A

公开(公告)日：2006-06-30

申请号：MYPI9905231

申请日：1999-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTINOU ,  CABRAL CYRIL JR ,  PARKS CHRISTOPHER CARR ,  RODBELL KENNETH PARKER ,  TSAI ROGER-YEN-LUEN

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/288 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: A METHOD FOR FORMING A COPPER CONDUCTOR (56, 58) IN AN ELECTRONIC STRUCTURE (50) BY FIRST DEPOSITING A COPPER COMPOSITION (88, 90, 100) IN A RECEPTACLE FORMED IN THE ELECTRONIC STRUCTURE, AND THEN ADDING IMPURITIES INTO THE COPPER COMPOSITION SUCH THAT ITS ELECTROMIGRATION RESISTANCE IS IMPROVED IS DISCLOSED. IN THE METHOD, THE COPPER COMPOSITION CAN BE DEPOSITED BY A VARIETY OF TECHNIQUES SUCH AS ELECTROPLATING, PHYSICAL VAPOR DEPOSITION AND CHEMICAL VAPOR DEPOSITION. THE IMPURITIES WHICH CAN BE IMPLANTED INCLUDE THOSE OF C, O, CI, S AND N AT A SUITABLE CONCENTRATION RANGE BETWEEN ABOUT 0.01 PPM BY WEIGHT AND ABOUT 1000 PPM BY WEIGHT.THE IMPURITIES CAN BE ADDED BY THREE DIFFERENT METHODS. IN THE FIRST METHOD, A COPPER SEED LAYER IS FIRST DEPOSITED INTO A RECEPTACLE AND AN ION IMPLANTATION PROCESS IS CARRIED OUT ON THE SEED LAYER, WHICH IS FOLLOWED BY ELECTROPLATING COPPER INTO THE RECEPTACLE. IN THE SECOND METHOD, A COPPER SEED LAYER IS FIRST DEPOSITED INTO A RECEPTACLE, A COPPER COMPOSITION CONTAINING IMPURITIES IS THEN ELECTRODEPOSITED INTO THE RECEPTACLE AND THE ELECTRONIC STRUCTURE IS ANNEALED SO THAT IMPURITIES DIFFUSE INTO THE COPPER SEED LAYER. IN THE THIRD METHOD, A BARRIER LAYER (82, 94) IS FIRST DEPOSITED INTO A RECEPTACLE, DOPANT IONS ARE THEN IMPLANTED INTO THE BARRIER LAYER WITH A COPPER SEED LAYER (84, 96) SUBSEQUENTLY DEPOSITED ON TOP OF THE BARRIER LAYER. AN ANNEALING PROCESS FOR THE ELECTRONIC STRUCTURE IS THEN CARRIED OUT SUCH THAT DOPANT IONS DIFFUSE INTO THE COPPER SEED LAYER. THE PRESENT INVENTION METHOD MAY FURTHER INCLUDE THE STEP OF ION-IMPLANTING AT LEAST ONE ELEMENT INTO A SURFACE LAYER OF THE COPPER CONDUCTOR (90, 100) AFTER THE CONDUCTOR IS FIRST PLANARIZED. THE SURFACE LAYER MAY HAVE A THICKNESS BETWEEN ABOUT 30 A AND ABOUT 500 A. AT LEAST ONE ELEMENT MAY BE SELECTED FROM CO, AI, SN, IN, TI AND CR.FIG. 2

公开(公告)号：DE10393309T5

公开(公告)日：2005-12-29

申请号：DE10393309

申请日：2003-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CABRAL CYRIL JR ,  IGGULDEN ROY C ,  MCSTAY IRENE LENNOX ,  CLEVENGER LAWRENCE A ,  WANG YUN YU ,  WONG KEITH KWONG HON ,  ROBL WERNER ,  GLUSCHENKOV OLEG ,  MALIK RAJEEV ,  SCHUTZ RONALD J

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A conductive structure in an integrated circuit ( 12 ), and a method of forming the structure, is provided that includes a polysilicon layer ( 30 ), a thin layer containing titanium over the polysilicon, a tungsten nitride layer ( 34 ) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region ( 38 ) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer ( 30 ) and the tungsten layer ( 32 ), and provides low interface resistance between the tungsten layer and the polysilicon layer.

公开(公告)号：AU2003273328A8

公开(公告)日：2004-04-08

申请号：AU2003273328

申请日：2003-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE ,  SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A conductive structure in an integrated circuit ( 12 ), and a method of forming the structure, is provided that includes a polysilicon layer ( 30 ), a thin layer containing titanium over the polysilicon, a tungsten nitride layer ( 34 ) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region ( 38 ) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer ( 30 ) and the tungsten layer ( 32 ), and provides low interface resistance between the tungsten layer and the polysilicon layer.

公开(公告)号：ES2136148T3

公开(公告)日：1999-11-16

申请号：ES94115744

申请日：1994-10-06

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ALFRED ,  D HEURLE FRANCOIS MAX ,  HARPER JAMES MCKELL EDWIN ,  MANN RANDY WILLIAM ,  MILES GLEN LESTER

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  C30B1/00

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.

公开(公告)号：AT183251T

公开(公告)日：1999-08-15

申请号：AT94115744

申请日：1994-10-06

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ALFRED ,  D HEURLE FRANCOIS MAX ,  HARPER JAMES MCKELL EDWIN ,  MANN RANDY WILLIAM ,  MILES GLEN LESTER ,  RAKOWSKI DONALD WALTER DOUGLAS

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  C30B1/00

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.