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    DEVICE CONTACT STRUCTURE AND METHOD FOR FABRICATING SAME.
    31.
    发明专利
    DEVICE CONTACT STRUCTURE AND METHOD FOR FABRICATING SAME. 未知

    公开(公告)号：MY121099A

    公开(公告)日：2005-12-30

    申请号：MYPI9904205

    申请日：1999-09-29

    Applicant: IBM

    Inventor： ALLEN ARCHIBALD J ,  FURUKAWA TOSHIHARU ,  O'NEIL EDWARD F ,  HAKEY MARK C ,  VERHELST ROGER A ,  HORAK DAVID V

    IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/11

    Abstract: THE PRESENT INVENTION OVERCOMES THE DIFFICULTIES FOUND IN THE BACKGROUND ART BY PROVIDING A DIRECT LOW RESISTIVE CONTACT (101, 102) BETWEEN DEVICES ON A SEMICONDUCTOR CHIP WITHOUT EXCESSIVE CURRENT LEAKAGE. CURRENT LEAKAGE IS PREVENTED IN THE PREFERRED DESIGN BY USING SILICON ON INSULATOR (SOI) CONSTRUCTION FOR THE CHIP. BY CONSTRUCTING THE DIRECT CONTACT OVER AN INSULATOR, SUCH AS SILICON DIOXIDE, CURRENT LEAKAGE IS MINIMIZED. THE PREFERRED EMBODIMENT USES SILICIDE (145, 147) TO CONNECT A POLYSILICON GATE (120, 122) TO A DOPED REGION (230, 235, 237, 830, 835, 837) OF THE SUBSTRATE. AN ALTERNATIVE EMBODIMENT OF THE PRESENT INVENTION PROVIDES FOR THE USE OF CONDUCTIVE STUDS (1910, 1920) TO ELECTRICALLY CONNECT DEVICES. AN INCREASED DENSITY OF APPROXIMATELY TWENTY PERCENT MAY BE REALIZED USING THE PRESENT INVENTION.

    A METHOD FOR FORMING SELF-ALIGNED FEATURES
    33.
    发明专利
    A METHOD FOR FORMING SELF-ALIGNED FEATURES 未知

    公开(公告)号：MY118631A

    公开(公告)日：2004-12-31

    申请号：MYPI9904305

    申请日：1999-10-06

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

    IPC: H01L21/4763 ,  H01L21/027 ,  H01L21/768

    Abstract: THE PRESENT INVENTION PROVIDES FOR AN IMPROVED METHOD OF CREATING VIAS (730, 735) AND TRENCHES (737-739) DURING MICROCHIP FABRICATION. ACCORDING TO THE INVENTION, THE VIAS AND TRENCHES ARE SELF-ALIGNED DURING THE PHOTOLITHOGRAPHY PROCESS BY USING TWO LAYERS OF SPECIALLY SELECTED RESISTS (205, 210, 1804, 1806) AND EXPOSING THE RESISTS SUCH THAT THE LOWER RESIST IS EXPOSED ONLY WHERE AN OPENING HAS BEEN FORMED IN THE UPPER RESIST LAYER. THIS SELF-ALIGNING ENABLES THE VIAS TO BE PRINTED AS ELONGATED SHAPES, WHICH ALLOWS FOR THE USE OF PARTICULARLY EFFECTIVE IMAGE ENHANCEMENT TECHNIQUES. THE INVENTION FURTHER PROVIDES A SIMPLIFIED PROCEDURE FOR CREATING VIAS AND TRENCHES, IN THAT ONLY ONE ETCH STEP IS REQUIRED TO SIMULTANEOUSLY CREATE BOTHVIAS AND TRENCHES. AN ALTERNATIVE EMBODIMENT OF THE INVENTION ALLOWS LOOPED OR LINKED IMAGES, SUCH AS THOSE PRINTED USING IMAGE ENHANCEMENT TECHNIQUES, TO BE TRIMMED TO FORM ISOLATED FEATURES.

    METHOD AND APPARATUS FOR ENHANCING THE DEPTH OF FOCUS IN PROJECTION LITHOGRAPHY
    36.
    发明专利
    METHOD AND APPARATUS FOR ENHANCING THE DEPTH OF FOCUS IN PROJECTION LITHOGRAPHY 未知

    公开(公告)号：CA2037705A1

    公开(公告)日：1991-10-19

    申请号：CA2037705

    申请日：1991-03-07

    Applicant: IBM

    Inventor： HAKEY MARK C ,  HORAK DAVID V ,  RATH PETER C

    IPC: G03F1/00 ,  G03F7/20 ,  G03F7/207 ,  H01L21/027 ,  H01L21/30

    Abstract: METHOD AND APPARATUS FOR ENHANCING THE DEPTH OF FOCUS IN PROJECTION LITHOGRAPHY The invention provides a technique which enables projection lithography to extend to the sub-half micron range by compensating the Depth of Focus (DOF) budget lost in substrate topography with a projection of a non-planar image which is conformal to the substrate. The method of achieving a non-planar image field includes the formation of a mask reticle which is a replica of the surface of the semiconductor to be exposed, thus, eliminating substrate topography from the optical DOF budget.

    37.
    发明专利
    未知

    公开(公告)号：DE60233241D1

    公开(公告)日：2009-09-17

    申请号：DE60233241

    申请日：2002-08-29

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H ,  RABIDOUX PAUL A

    IPC: H01L29/76 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    Abstract: A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

    Apparatus and method for self-aligning optical fiber to optical waveguide
    38.
    发明专利
    Apparatus and method for self-aligning optical fiber to optical waveguide 未知

    公开(公告)号：HK1063849A1

    公开(公告)日：2005-01-14

    申请号：HK04106477

    申请日：2004-08-28

    Applicant: IBM

    Inventor： GERMANN ROLAND ,  HORAK DAVID V ,  SEKIGUCHI AKIHISA

    IPC: G02B6/30 ,  G02B ,  H01L

    Abstract: An apparatus for self-aligning an optical fiber to an optical waveguide. The apparatus includes an optical waveguide chip including: one or more optical waveguides formed on a first substrate, each optical waveguide having a protruding portion; and one or more alignment rails formed on the first substrate, each alignment rail spaced apart from each optical waveguide by a predetermined distance; and an alignment jig including: one or more grooves formed in a second substrate, each groove adapted to receive one protruding portion and each groove supporting one optical fiber in alignment with one optical waveguide; and one or more alignment grooves formed on the second substrate, each alignment groove spaced apart from the grooves by the predetermined distance and adapted to mate with the alignment rails.

    PROCESS FOR SELF-ALIGNMENT OF SUB-CRITICAL CONTACTS TO WIRING
    39.
    发明专利
    PROCESS FOR SELF-ALIGNMENT OF SUB-CRITICAL CONTACTS TO WIRING 未知

    公开(公告)号：MY117201A

    公开(公告)日：2004-05-31

    申请号：MYPI9904530

    申请日：1999-10-20

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

    IPC: G03C5/00 ,  H01L21/28 ,  H01L21/027 ,  H01L21/302 ,  H01L21/32 ,  H01L21/60 ,  H01L21/768

    Abstract: A METHOD FOR FORMING CONTACTS ON AN INTEGRATED CIRCUIT THAT ARE SELF-ALIGNED WITH THE WIRING PATTERNS OF THE INTEGRATED CIRCUIT. IN THE METHOD A THICKER LOWER LAYER (12) OF A FIRST MATERIAL AND A THINNER UPPER LAYER (14) OF A SECOND MATERIAL ARE FORMED ON A SUBSTRATE (10). THE FEATURES OF THE METAL WIRING IS PATTERNED FIRST ON THE UPPER LAYER. THE WIRING PATTERN TRENCHES (20) ARE ETCHED THROUGH THE THINNER SURFACE LAYER, AND PARTIALLY THROUGH THE SECOND, THICKER LAYER. AFTER THE WIRING PATTERN IS ETCHED, THE CONTACTS FOR THE WIRING LAYER ARE PRINTED AS LINE/SPACE PATTERNS WHICH INTERSECT THE WIRING PATTERN. THE CONTACT PATTERN IS ETCHED INTO THE LOWER, THICKER LAYER WITH AN ETCH PROCESS THAT IS SELECTIVE TO THE UPPER THINNER LAYER. THE CONTACT IS ONLY FOFFI1ED AT THE INTERSECTION POINT OF THE WIRING IMAGE WITH THE CONTACT IMAGE, THEREFORE THE CONTACT IS SELF-ALIGNED TO THE METAL (24).

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