公开(公告)号：GB2504032A

公开(公告)日：2014-01-15

申请号：GB201318585

申请日：2010-08-23

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  OUYANG XU ,  YANG CHIH-CHAO

IPC: H01L27/06

Abstract: A modularized capacitor array includes a plurality of stacked capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates where the middle electrode is shared between capacitors. In some embodiments each module 4 comprises at least two capacitors C1:C6 comprising at least three overlapping conductive plates 10, 20, 30:70. Each switch can comprise a field effect transistor, FET. In some embodiments each module comprises a capacitor-side via that contacts at least one plate of the capacitors and the switching device.

公开(公告)号：GB2486115B

公开(公告)日：2013-12-18

申请号：GB201204298

申请日：2010-08-23

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  OUYANG XU ,  YANG CHIH-CHAO

IPC: G11C11/24 ,  G11C11/34

Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

公开(公告)号：DE602006008984D1

公开(公告)日：2009-10-15

申请号：DE602006008984

申请日：2006-12-05

Applicant: IBM

Inventor： MANDELMAN JACK ALLAN ,  CHENG KANGGUO ,  HSU LOUIS LU-CHEN ,  YANG HAINING

IPC: H01L29/786 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/78

Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

公开(公告)号：DE10196673T1

公开(公告)日：2003-08-28

申请号：DE10196673

申请日：2001-09-21

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  PARENT RICHARD MICHAEL ,  WORDEMAN MATTHEW R

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4074

Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.

公开(公告)号：DE69302359D1

公开(公告)日：1996-05-30

申请号：DE69302359

申请日：1993-09-21

Applicant: IBM

Inventor： HUANG DANIEL L ,  HSU LOUIS LU-CHEN ,  WANG WEN-YUAN

IPC: H01L21/336 ,  H01L29/78

公开(公告)号：DE10196673B4

公开(公告)日：2008-01-31

申请号：DE10196673

申请日：2001-09-21

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  PARENT RICHARD MICHAEL ,  WORDEMAN MATTHEW R

IPC: G11C8/08 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4074

Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.

公开(公告)号：ES2262810T3

公开(公告)日：2006-12-01

申请号：ES02732895

申请日：2002-05-15

Applicant: IBM

Inventor： CHEN HOWARD HAO ,  HSU LOUIS LU-CHEN ,  WANG LI-KONG

IPC: G01R31/28 ,  G06F11/27 ,  G01R31/3187 ,  G06F11/22 ,  H01L21/822 ,  H01L27/04

Abstract: Un aparato para proporcionar autocomprobación integrada jerárquica para un sistema con chip, comprendiendo dicho aparato: un controlador BIST central; una pluralidad de circuitos BIST locales comprendiendo cada uno al menos un macro y al menos un generador de imagen de prueba para generar imágenes de prueba predefinidas; y al menos un medio de comunicación para realizar operaciones de control y transferencia entre dicho controlador BIST central y dicha pluralidad de circuitos BIST locales, realizando dicho controlador BIST central la prueba de los circuitos BIST locales en una forma jerárquica siguiendo un algoritmo de prueba jerárquico.

公开(公告)号：AT332530T

公开(公告)日：2006-07-15

申请号：AT02732895

申请日：2002-05-15

Applicant: IBM

Inventor： CHEN HOWARD HAO ,  HSU LOUIS LU-CHEN ,  WANG LI-KONG

IPC: G01R31/28 ,  G06F11/22 ,  G06F11/27 ,  H01L21/822 ,  H01L27/04 ,  G01R31/3187

Abstract: Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.

公开(公告)号：AU2003214978A1

公开(公告)日：2004-08-30

申请号：AU2003214978

申请日：2003-01-31

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  SELANDER KARL ,  SORNA MICHAEL ,  ZIER STEVEN J

IPC: H01L21/00 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/04 ,  H01L27/105 ,  H01L27/115 ,  H03K3/012 ,  H03K3/356 ,  H04B3/00 ,  H04L25/02 ,  H03K17/00 ,  H03K19/00 ,  H03K19/094 ,  H04B17/00

公开(公告)号：AU2002216238A1

公开(公告)日：2002-07-24

申请号：AU2002216238

申请日：2001-12-21

Applicant: IBM

Inventor： CABRAL CYRIL ,  HSU LOUIS LU-CHEN ,  WONG KEITH KWONG HON ,  CLEVENGER LAWRENCE

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/525 ,  H01L27/06 ,  H01L23/64

Abstract: A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.