公开(公告)号：EP1935020A4

公开(公告)日：2009-08-12

申请号：EP06825028

申请日：2006-09-19

Applicant: IBM

Inventor： BEINTNER JOCHEN ,  LUDWIG THOMAS ,  NOWAK EDWARD J

IPC: H01L21/84 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

公开(公告)号：EP1671376A4

公开(公告)日：2008-09-03

申请号：EP04785971

申请日：2004-06-30

Applicant: IBM

Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

IPC: H01L21/28 ,  H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.

Abstract translation: 场效应晶体管器件的多层栅电极堆叠结构形成在栅电介质（43）上的硅纳米晶种层（41）上。 使用原位快速热化学气相沉积（RTCVD），硅纳米晶体层的小晶粒尺寸允许沉积具有高达至少70％的[Ge]的均匀且连续的多晶SiGe（45）层。 在快速降低的温度下在氧气环境中原位净化沉积室导致SiO2或SixGeyOz薄界面层（47），（3）至4A厚。 薄SiO2或SixGeyOZ界面层足够薄且不连续以提供对栅极电流流动的小阻力，但具有足够的[O]以在热处理期间有效阻挡向上的Ge扩散，从而允许随后沉积的钴层发生硅化。 该栅极电极堆叠结构用于nFET和pFET。

公开(公告)号：EP1639648A4

公开(公告)日：2007-05-30

申请号：EP04777432

申请日：2004-06-30

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L29/06 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

公开(公告)号：EP1644968A4

公开(公告)日：2007-03-14

申请号：EP04777136

申请日：2004-06-25

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L21/336 ,  H01L20060101 ,  H01L21/20 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/036

CPC classification number: H01L29/785 ,  H01L21/2022 ,  H01L29/66795

Abstract: A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

公开(公告)号：JP2003249622A

公开(公告)日：2003-09-05

申请号：JP2003019022

申请日：2003-01-28

Applicant: IBM

Inventor： LASKY JEROME B ,  NOWAK EDWARD J ,  SPROGIS EDMUND J

IPC: H01L25/18 ,  H01L21/768 ,  H01L23/48 ,  H01L23/50 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To provide chip-on-chip module and a forming method belonging to the same. SOLUTION: A first semiconductor chip is connected to a second semiconductor chip. The first chip comprises a first wiring layer and a first conductive substrate in the first side and the second side of the first chip, respectively. A power supply voltage VDD is adapted so as to be electrically connected to the second side of the first chip. The second chip comprises a second wiring layer and a second conductive substrate in the first side and the second side of the second chip, respectively. A grounding voltage GND is adapted so as to be electrically connected to the second side of the second chip. The first side of the first chip is connected to the first side of the second chip. The power supply voltage VDD and the grounding voltage GND are adapted so as to supply an electric power to the first and the second chips. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003204068A

公开(公告)日：2003-07-18

申请号：JP2002361664

申请日：2002-12-13

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide an asymmetrical field effect transistor (FET) having a threshold voltage which is compatible with the present CMOS circuit design and a low-resistance gate electrode. SOLUTION: This asymmetrical FET contains a structure integrated with a p-type gate portion and an n-type gate portion provided on the main body of a vertical semiconductor and the interconnection between the gate portions and a flattened structure on the interconnection. Because of the integrated Fin FET/thick polycilicon-containing gate structure, an Fin FET having the threshold voltage which is compatible with the present CMOS circuit design and the gate electrode the resistivity of which is lower than that of the conventional symmetrical Fin FET can be manufactured. The asymmetrical FET contains the n-type gate portion and p-type gate portion on the main body of the vertical semiconductor and the interconnection between the gate portions and the flattened structure on the interconnection. COPYRIGHT: (C)2003,JPO

公开(公告)号：JPH11260909A

公开(公告)日：1999-09-24

申请号：JP1713999

申请日：1999-01-26

Applicant: IBM

Inventor： NOWAK EDWARD J ,  MIN HOO TON

IPC: H01L21/76 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To realize a decoupling capacitance permitted by a semiconductor device by forming a high junction capacitance while forming an implantation layer under an insulating layer of a first circuit region, and connecting the implantation layer to wells of a second circuit region. SOLUTION: An isolation oxide layer 22, a first device layer 24, an isolation layer 20, and a first polarity type highly doped implantated layer 25 that is formed under the layer 22 are formed at a first circuit region of an SOI structure. Further, a second circuit region (e.g. a bulk device region) is adjacent to the first circuit region, and has a bulk region 30, first polarity type wells 32 and 34, a second device region having regions 36, 38 and 42, a region 44 of first and second polarity type, the layer 20 and the like. Both circuit regions are located on a second polarity type substrate 50. The first circuit region covers almost the whole chip. If a larger capacitance is required, a second polarity type dopant 40 is used under the layer 25 formed by ion implantation with 1 MeV energy.

公开(公告)号：JP2010153787A

公开(公告)日：2010-07-08

申请号：JP2009227678

申请日：2009-09-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOWAK EDWARD J ,  BRENT A ANDERSON

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/11 ,  H01L29/786

CPC classification number: H01L21/823412

Abstract: PROBLEM TO BE SOLVED: To provide band edge controlled Vt offset devices.
SOLUTION: There are provided band edge controlled Vt offset devices, design structures for band edge controlled Vt offset devices and methods of manufacturing such structures. The structure includes a first FET having a channel of a first compound semiconductor of first atomic proportions resulting in a first band structure and a first type. The structure further includes a second FET having a channel of a second compound semiconductor of second atomic proportions resulting in a second band structure and a first type. The first compound semiconductor is different from the second compound semiconductor such that the first FET includes a first band structure different from second band structure, giving rise to a threshold voltage different from that of the second FET.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供带边缘控制的Vt偏移装置。 解决方案：提供带边缘控制的Vt偏移器件，用于带边缘控制的Vt偏移器件的设计结构以及制造这种结构的方法。 该结构包括具有第一原子比例的第一化合物半导体的通道的第一FET，其导致第一带结构和第一类型。 该结构还包括具有第二原子比例的第二化合物半导体的通道的第二FET，其导致第二带结构和第一类型。 第一化合物半导体与第二化合物半导体不同，使得第一FET包括与第二带结构不同的第一带结构，产生与第二FET不同的阈值电压。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008211214A

公开(公告)日：2008-09-11

申请号：JP2008041378

申请日：2008-02-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOWAK EDWARD J ,  BRENT A ANDERSON

IPC: H01L21/26 ,  H01L21/265 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor wafer structure which makes the interior of a wafer surface uniform in reflection factor, in order to acquire an uniform temperature change over a wafer whole region, when a rapid thermal annealing process of a semiconductor structure including a combination of different semiconductor materials is carried out. SOLUTION: In a semiconductor wafer structure in which a first device 401 includes epitaxial growth silicon germanium with a first reflection factor, and a second device 402 includes single crystal silicon with a second reflection factor, a uniform reflection factor is obtained by distributing a first device 451 as a non-functionality dummy including silicon germanium, and a second device 452 as a non-functionality dummy including single crystal silicon over the wafer whole region to obtain the same overall ratio and same density as a distribution of the first and the second device. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供使晶片内部的内部的反射系数均匀的半导体晶片结构的制造方法，为了在晶片整体区域上获得均匀的温度变化，当快速热退火 执行包括不同半导体材料的组合的半导体结构的工艺。 解决方案：在第一器件401包括具有第一反射因子的外延生长硅锗的第二器件402中，并且第二器件402包括具有第二反射系数的单晶硅的半导体晶片结构中，通过分布获得均匀的反射系数 作为包括硅锗的非功能虚拟的第一装置451和作为包括单晶硅的非功能虚拟的第二装置452在晶片整个区域上以获得与第一和第二装置451的分布相同的总比率和相同密度 第二个设备。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008172238A

公开(公告)日：2008-07-24

申请号：JP2008001417

申请日：2008-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOWAK EDWARD J ,  CLARK JR WILLIAM F

IPC: H01L29/786 ,  H01L29/861

CPC classification number: H01L29/861 ,  H01L29/402 ,  H01L29/417 ,  H01L29/6609 ,  H01L29/772 ,  H01L29/78648

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode).
SOLUTION: This field shield is sandwiched between upper and lower isolation layers 203, 204 on a wafer. A local interconnect 235 extends through the upper isolation layer 204 and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region 211, 212 of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer 204 and down into the field shield. Consequently, an electric charge 220 is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在半导体器件（例如场效应晶体管（FET）或二极管）之下并入场屏蔽的半导体结构。 解决方案：该场屏蔽夹在晶片上的上隔离层203和下隔离层204之间。 局部互连235延伸穿过上隔离层204并将场屏蔽连接到器件的选定掺杂半导体区域（例如，FET或二极管的阴极或阳极的源极/漏极区域211,212）。 进入设备的电流，例如，在线路充电的后端，被远离上隔离层204的本地互连分流并且下降到场屏蔽中。 因此，电荷220不允许在上部隔离层中积聚，而是从场屏蔽件渗入下部隔离层并进入下面的基板。 该场屏蔽进一步提供抵抗掉在下隔离层或衬底内的任何电荷的保护屏障。 版权所有（C）2008，JPO＆INPIT