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    GATE STRUCTURE OF SEMICONDUCTOR DEVICE
    31.
    发明专利
    GATE STRUCTURE OF SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：JP2002124672A

    公开(公告)日：2002-04-26

    申请号：JP2001193470

    申请日：2001-06-26

    Applicant: IBM

    Inventor： CLEVENGER LAWRENCE ALFRED ,  MANDELMAN JACK A ,  JAMMY RAJARO ,  GLUSCHENKOV OLEG ,  MCSTAY IRENE LENNOX ,  WONG KWONG HON ,  FALTERMEIER JONATHAN

    IPC: H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide a gate structure for MOSFETs for application of the CMOS technology, etc., which is durable against high temperature processes such as junction activation, etc., and reduces the gate propagation delay. SOLUTION: The gate structure 10 has an insulation layer 14 on a semiconductor substrate 12, and a polysilicon gate electrode 16 on the insulation layer 14. The gate structure 10 comprises a diffused barrier layer 20 having semi- insulative characteristics on the gate electrode 16, and a gate conductor 18 on the barrier layer 20. The conductor 18 is electrically contacted to the gate electrode 16. The constitution and the thickness of the barrier layer 20 are adjusted so as to effectively block the diffusion and the mixing between the gate conductor 18 and the gate electrode 16, but realize a capacitive coupling and/or a leak current not so increasing the gate propagation delayer of the gate surface 10.

    MULTIPLE LOW AND HIGH K GATE OXIDES ON SINGLE GATE FOR LOWER MILLER CAPACITANCE AND IMPROVED DRIVE CURRENT
    32.
    发明申请
    MULTIPLE LOW AND HIGH K GATE OXIDES ON SINGLE GATE FOR LOWER MILLER CAPACITANCE AND IMPROVED DRIVE CURRENT 审中-公开
    在单闸门上多个低K和高K门氧化物用于较低的电容和改进的驱动电流

    公开(公告)号：WO2007038237A3

    公开(公告)日：2007-07-26

    申请号：PCT/US2006036916

    申请日：2006-09-22

    Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

    Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

    IPC: H01L21/28 ,  H01L29/40

    CPC classification number: H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

    Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i-e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, and the first gate oxide is higher k than the second gate oxide or vice-versa.

    Abstract translation: 本发明提供一种半导体结构，其具有至少一个CMOS器件，其中米勒电容，即重叠电容，并且驱动电流得到改善。 本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。 根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，并且第一栅极氧化物比第二栅极氧化物高k，反之亦然 。

    METHOD OF ENHANCED OXIDATION OF MOS TRANSISTOR GATE CORNERS
    34.
    发明申请
    METHOD OF ENHANCED OXIDATION OF MOS TRANSISTOR GATE CORNERS 审中-公开
    MOS晶体管栅极的增强氧化方法

    公开(公告)号：WO02089180A3

    公开(公告)日：2003-02-06

    申请号：PCT/US0149571

    申请日：2001-12-27

    Applicant: IBM

    Inventor： DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G ,  KAPLAN RICHARD ,  KHARE MUKESH

    IPC: H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/31

    CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/4941

    Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners (20) of a Si-containing transistor having a gate conductor (16) and a dielectric cap (18), and exposing the transistor including implanted transistor gate corners (20) to an oxidizing ambient. The ions employed in the implant step include Si, non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, C1, He, Ar, Kr, and Xe; and mixtures thereof.

    Abstract translation: 提供了一种提高晶体管栅极角氧化速率的方法，而不显着增加整体处理方案的热预算。 具体地，本发明的方法包括将离子注入到具有栅极导体（16）和电介质盖（18）的含硅晶体管的栅极拐角（20）中，并且使包括注入的晶体管栅极角（20）的晶体管暴露， 到氧化环境。 在注入步骤中使用的离子包括Si，不延迟氧化离子如O，Ge，As，B，P，In，Sb，Ga，F，Cl，He，Ar，Kr和Xe; 及其混合物。

    SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD
    35.
    发明申请
    SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD 审中-公开
    硅锗绝缘双极晶体管结构与方法

    公开(公告)号：WO2008134686A3

    公开(公告)日：2009-12-30

    申请号：PCT/US2008061938

    申请日：2008-04-30

    Applicant: IBM ,  KRISHNASAMY RAJENDRAN ,  GLUSCHENKOV OLEG ,  SCHONENBERG KATHRYN T

    Inventor： KRISHNASAMY RAJENDRAN ,  GLUSCHENKOV OLEG ,  SCHONENBERG KATHRYN T

    IPC: H01L21/331

    CPC classification number: H01L29/66242 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

    Abstract: Disclosed is an improved semiconductor structure 150 (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor 100) having a narrow essentially interstitial-free SIC pedestal 120 with minimal overlap of the extrinsic base 104. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base 103 and collector space-charge regions than can be achieved with conventional technology.

    Abstract translation: 公开了一种改进的半导体结构150（例如，硅锗（SiGe）异质结双极晶体管100），其具有窄的基本上无间隙的SIC基座120，其外部基极104具有最小的重叠。此外，公开了一种形成 使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本上无间隙的收集器的晶体管。 因此，所得到的SiGe HBT晶体管可以制造成具有比用常规技术可以实现的更窄的基极103和集电极空间电荷区域。

    EPITAXY OF SILICON-CARBON SUBSTITUTIONAL SOLID SOLUTIONS BY ULTRA-FAST ANNEALING OF AMORPHOUS MATERIAL
    36.
    发明申请
    EPITAXY OF SILICON-CARBON SUBSTITUTIONAL SOLID SOLUTIONS BY ULTRA-FAST ANNEALING OF AMORPHOUS MATERIAL 审中-公开
    通过超弹性非晶态材料退火的硅碳取代固体溶液外延

    公开(公告)号：WO2007112432A3

    公开(公告)日：2009-03-26

    申请号：PCT/US2007065324

    申请日：2007-03-28

    Applicant: IBM ,  LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

    Inventor： LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

    IPC: H01L21/20 ,  H01L21/36

    CPC classification number: H01L21/2022 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

    Abstract: Expitaxial substitutional solid solutions of silicon carbon (101 ) can be obtained by an ultra-fast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials (101 ) with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si1-yCy, y

    Abstract translation: 可以通过非晶态含碳硅材料的超快速退火获得硅碳（101）的外延替代固溶体。 退火在高于再结晶点的温度下进行，但低于材料的熔点，并且在该温度范围内优选持续小于100毫秒。 退火优选是闪光退火或激光退火。 该方法能够产生具有替代晶格位置的大部分碳原子的外延硅和含碳材料（101）。 该方法在CMOS工艺和其他电子器件制造中特别有用，其中外延Si1-yCy，y <0.1对于应变工程或带隙工程是需要的。

    DUAL STRESSED SOI SUBSTRATES
    37.
    发明申请
    DUAL STRESSED SOI SUBSTRATES 审中-公开
    双应力SOI衬底

    公开(公告)号：WO2006065759A3

    公开(公告)日：2007-06-14

    申请号：PCT/US2005044957

    申请日：2005-12-13

    Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

    Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

    IPC: H01L21/84 ,  H01L27/01

    CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

    Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

    Abstract translation: 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠 所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

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