公开(公告)号：DE10323237A1

公开(公告)日：2004-12-16

申请号：DE10323237

申请日：2003-05-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BREDE RUEDIGER ,  FISCHER HELMUT ,  SAVIGNAC DOMINIQUE

IPC: G11C7/10 ,  G11C11/4076 ,  G11C29/50

Abstract: The method involves producing a real time period in the memory during a test mode. The real time period is selected so that a performance parameter of the memory improves between the execution time-points of two operations. The set time period is changed in the direction of the real time period in the test mode, and information relating to the modified set time period is stored in the memory. An independent claim is included for a semiconductor memory device.

公开(公告)号：DE10242817C1

公开(公告)日：2003-12-04

申请号：DE10242817

申请日：2002-09-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/407

Abstract: The memory circuit has at least one memory bank (10) divided into several regions, the memory cell columns in each region divided into segments, with a respective bus (26a,26b) for each region and a bundle of master datalines (ML) for each segment, coupled to a line network for addressing the individual memory cells. The region buses are cyclically coupled to a common data port (22) via a multiplexer (23), a control device (30) for the read and write operations allowing the beginning of a read phase to overlap the end of a write phase. A data latch (28) is coupled to each master dataline for holding the applied data group, a separation switch (27) controlled by the control device allowing the master datalines to be separated from the region bus. An Independent claim for an operating method for a random-access memory circuit is also included.

公开(公告)号：DE10201179A1

公开(公告)日：2003-08-14

申请号：DE10201179

申请日：2002-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MENCZIGAR ULLRICH ,  PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C7/10 ,  G11C11/407

Abstract: The circuit has at least two pairs of adjacent banks, a bundle of input/output lines, a controller and a changeover device. Only two bundles of read/write data lines are provided per pair of adjacent memory banks, the first associated with the first and second halves of the first and second banks and the second with the second and first halves of the first and second banks. The circuit has at least two pairs of adjacent banks (BK00-BK11), each with a number of memory cells in each bank, a bundle of input/output lines, a controller (120) and a changeover device (30) controllable depending on a clock signal for connecting the input/outputs lines to the first and second halves of the addressed memory bank during first and second half periods. Only two bundles (LDa,b) of read/write data lines are provided per pair of adjacent memory banks, the first associated with the first and second halves of the first and second banks and the second with the second and first halves of the first and second banks.

公开(公告)号：DE10159798A1

公开(公告)日：2003-07-17

申请号：DE10159798

申请日：2001-12-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  FISCHER HELMUT

IPC: G11C11/408 ,  G11C8/00 ,  G11C8/08

公开(公告)号：DE10145727A1

公开(公告)日：2003-04-17

申请号：DE10145727

申请日：2001-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  H01L21/822 ,  H01L27/04 ,  G01R31/3187

Abstract: A test module (30) set up for testing an electronic circuit connects to a wire (38,40) and/or a connector for the electronic circuit. A test control signal (34) is generated, with which the test module in an operating module for the electronic circuit is decoupled from the wire or the connector in such a way that switching currents are avoided in the test module. An Independent claim is also included for a device for reducing power consumption in an electronic circuit.

公开(公告)号：DE10107314C2

公开(公告)日：2003-03-27

申请号：DE10107314

申请日：2001-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT

IPC: G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C7/12

Abstract: In a semiconductor memory, there is capacitive coupling between bit lines that largely run in parallel. Outer sections of the bit lines are connected via respective switches to a sense amplifier arranged between the switches. When a memory cell is being read, the capacitive interference by other bit lines that are not coupled to the memory cell being read is kept as low as possible before the start of amplification by the sense amplifier by turning on the switches in that bit line. During the amplification phase, the remote outer section of that bit line is disconnected using the appropriate switch. In one embodiment, the capacitance of the bit line that is not connected to the memory cell to be read is increased further by additionally activating a precharging circuit.

公开(公告)号：DE10125371A1

公开(公告)日：2002-12-12

申请号：DE10125371

申请日：2001-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT ,  SZCZYPINSKI KAZIMIERZ ,  BENEDIX ALEXANDER

IPC: G11C7/10 ,  G11C7/22

公开(公告)号：DE10051613C2

公开(公告)日：2002-10-24

申请号：DE10051613

申请日：2000-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  CHRISSOSTOMIDIS IOANNIS ,  SCHAFFROTH THILO

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C11/4091 ,  G11C5/14

Abstract: The circuit has a first current path for activation of the memory via an addressed word line, a second current path in which a read amplifier control signal is generated by a controler from a signal (RAVLD) derived from the first current path and a voltage supply device for components of the two current paths. Thick oxide transistors (T) supplied with an increased supply voltage are provided in the second path in addition to thin oxide transistors (T') supplied with a normal voltage.

公开(公告)号：DE10038665C1

公开(公告)日：2002-03-14

申请号：DE10038665

申请日：2000-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  SCHNABEL JOACHIM

IPC: G11C8/00 ,  G11C8/08 ,  G11C29/00 ,  G11C7/00

Abstract: The circuit has a control stage that produces a deactivation control signal in response to a deactivation command to set a controllable connection device in the conducting state. A selectively switched reducing device limits the current flowing via the conducting connecting device in the on state so that the total current flowing in a common line system providing a deactivation potential does not exceed a defined value. The circuit has a control stage (2) that produces a deactivation control signal in response to a deactivation command to set a controllable connection device (T2), which is provided for each word line (WL) for connecting it to a common line system (DL) for providing a deactivation potential, in the conducting state. A selectively switched reducing device (T7-T9, HL) limits the current flowing via the conducting connecting device in the on state so that the total current flowing in the common line system does not exceed a defined value.

公开(公告)号：DE10034928A1

公开(公告)日：2002-02-07

申请号：DE10034928

申请日：2000-07-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G06F11/20 ,  G11C29/00 ,  G11C17/16

Abstract: The invention relates to a configuration for implementing redundancy for a memory chip, in which a fuse bank is connected to a comparator via a redundancy predecoder so that predecoded addresses can be compared with one another in the comparator and undecoded addresses can be stored in the fuse bank. This provides for a low-power and space-saving design.