中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

85 records (took 0.028 seconds)

    32.
    发明专利
    未知

    公开(公告)号：DE102004047751B3

    公开(公告)日：2006-05-04

    申请号：DE102004047751

    申请日：2004-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOLDBACH MATTHIAS

    IPC: H01L21/8242

    Abstract: A method for fabricating transistor structures for DRAM semiconductor components includes forming gate conductor structures in a cell array of a DRAM semiconductor component and covering the structures with a spacer liner. The gate conductor structures lie on a silicon semiconductor substrate. A masked spacer etch produces a spacer mask with horizontal sections and vertical spacer structures from the spacer liner for aligning implantation steps and for self-aligned formation of silicide structures at the surface of the semiconductor substrate. A CB contact implantation step is provided prior to the filling of trenches between the gate conductor structures with dielectric silicate glass fillings, and this obviates the need for an isolated high-temperature activation anneal for the CB contact implantation as well as reducing the thermal stresses on regions of the semiconductor substrate which have already been doped. A reflow heating step for partially melting the silicate glass is controlled as a final furnace anneal for annealing lattice defects in the semiconductor substrate. The contact resistance of a bit contact structure is lowered, while at the same time the thermal stresses are reduced.

    33.
    发明专利
    未知

    公开(公告)号：DE10211932B9

    公开(公告)日：2006-03-30

    申请号：DE10211932

    申请日：2002-03-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS

    IPC: G11C7/06 ,  G11C11/4091 ,  G11C29/00 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50 ,  H03F3/195

    Abstract: A circuit arrangement includes a bit line ( 10 ), a reference bit line ( 12 ), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor ( 20, 22 ) and a p-channel field-effect transistor ( 30, 32 ), and also, at the respective source terminals, two voltage sources ( 40, 42 ), of which the voltage source ( 40 ) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source ( 42 ) linked to the p-channel field-effect transistors ( 30, 32 ) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell ( 4 ) on the bit line ( 10 ) if the threshold voltages (U TH1 , U TH2 ) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell ( 4 ).

    34.
    发明专利
    未知

    公开(公告)号：DE102004005992B3

    公开(公告)日：2005-11-17

    申请号：DE102004005992

    申请日：2004-02-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FREY ULRICH ,  GOLDBACH MATTHIAS ,  OFFENBERG DIRK

    IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8239 ,  H01L27/085 ,  H01L27/105 ,  H01L29/49 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

    Abstract: The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps: provision of a semiconductor substrate ( 1 ) with a gate dielectric ( 5 ); provision of a plurality of multilayered, elongate gate stacks (GS 1; GS 2 ) which essentially run parallel to one another on the gate dielectric ( 5 ), which gate stacks have a bottommost layer ( 10 ) made of silicon; provision of a first liner layer ( 60 ) made of a first material over the gate stacks (GS 1; GS 2 ) and the gate dielectric ( 5 ) uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h') of the bottommost layer ( 10 ) made of silicon; provision of sidewall spacers ( 70 ) made of a second material on the vertical sidewalls of the gate stacks (GS 1; GS 2 ) over the first liner layer ( 60 ), a region of the first liner layer ( 60 ) over the gate dielectric ( 5 ) between the gate stacks (GS 1; GS 2 ) remaining free; selective removal of the first liner layer ( 60 ) with respect to the sidewall spacers ( 70 ) for the purpose of laterally uncovering the bottommost layer ( 10 ) made of silicon of the gate stacks (GS 1; GS 2 ); and selective oxidation of the uncovered bottommost layer ( 10 ) for the purpose of forming sidewall oxide regions ( 50 ') on the gate stacks (GS 1; GS 2 ).

    35.
    发明专利
    未知

    公开(公告)号：DE10211932B4

    公开(公告)日：2005-09-15

    申请号：DE10211932

    申请日：2002-03-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS

    IPC: G11C7/06 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50 ,  G11C29/00 ,  H03F3/195

    Abstract: A circuit arrangement includes a bit line ( 10 ), a reference bit line ( 12 ), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor ( 20, 22 ) and a p-channel field-effect transistor ( 30, 32 ), and also, at the respective source terminals, two voltage sources ( 40, 42 ), of which the voltage source ( 40 ) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source ( 42 ) linked to the p-channel field-effect transistors ( 30, 32 ) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell ( 4 ) on the bit line ( 10 ) if the threshold voltages (U TH1 , U TH2 ) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell ( 4 ).

    36.
    发明专利
    未知

    公开(公告)号：DE10138981B4

    公开(公告)日：2005-09-08

    申请号：DE10138981

    申请日：2001-08-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS

    IPC: H01L21/3063 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242

    Abstract: In a process for the electrochemical oxidation of a semiconductor substrate that has recesses, such as for example, capacitor trenches or mesopores, formed in a silicon surface region, self-limited oxide formation takes place. The end of this formation is reached as a function of the process parameters such as the doping of the silicon region, the applied voltage and the composition of the electrolyte used, as soon as either a predetermined maximum layer thickness of the formed oxide or a predetermined minimum residual silicon layer thickness between two adjacent recesses is reached. The self-limiting is achieved either as a result of the overall voltage applied over the silicon oxide layer, which has already formed, dropping or as a result of the space charge regions of adjacent recesses coming into contact with one another.

    37.
    发明专利
    未知

    公开(公告)号：DE10356476B3

    公开(公告)日：2005-06-30

    申请号：DE10356476

    申请日：2003-12-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  SCHUSTER THOMAS ,  MUELLER RALF ,  KIESLICH ALBRECHT ,  ALSMEIER JOHANN ,  OFFENBERG DIRK ,  GOLDBACH MATTHIAS

    IPC: H01L27/108 ,  H01L21/265 ,  H01L21/8242

    Abstract: A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

Patent Agency Ranking