公开(公告)号：FR2846464A1

公开(公告)日：2004-04-30

申请号：FR0213497

申请日：2002-10-29

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE

IPC: G11C11/56 ,  G11C17/14 ,  G11C17/08 ,  G11C17/18 ,  H01L27/115

Abstract: The memory cell or point memory which is of electrically programmable read-only type comprises a MOS transistor with the gate oxide layer (14) and the gate (G) which is electrically connected. In programming operation the gate oxide layer (14) is degraded at least locally at point Z so to obtain in the reading operations a variation of current (Id) delivered by the transistor. The MOS transistor is a transistor with thin gate oxide layer (GO1), whose thickness is substantially equal to 2.5 nm. The gate oxide layer (14) is degraded as a function of used programming voltages. The degradation of the gate oxide layer is implemented in the full length of transistor channel (12), or in the vicinity of at least one electrode, source (S) and drain (D), in particular the drain electrode. A method (claimed) for programming the memory cell (claimed) consists of applying the programming voltages to the transistor electrodes which cause an irreversible degradation of the gate oxide layer of the transistor so that the read current (Id) is varied. In the course of programming the gate voltage is equal to at least 1.2 V, the voltage between the source and the drain is equal to about 3 V, and the bulk voltage is negative and qual to about -1 V. A method (claimed) for reading the memory cell consists of applying between the drain and the source a voltage in the range from 0.1 V to 1.2 V. An integrated circuit (claimed) comprises a central part with MOS transistors having the thin gate oxide layer (GO1) and a peripheral part with MOS transistors having a thicker gate oxide layer (GO2). The central part comprises a flat memory comprising memory cells with the MOS transistors having the thin gate oxide layer. In the write operation the programming voltages are applied to cause the degradation of the gate oxide layer of the selected transistor. A higher programming voltage is applied either to the drain or to the source of the memory cell so to cause degradations in the respective zones of the gate oxide layer. Each memory cell is also associated with another transistor allowing an adjustment of the source voltage of non-selected transistors. The thickness of the thicker gate oxide layer is substantially equal to 7 nm. The lower and the higher supply voltages are about 1.2 V and 3.3 V, respectively.

公开(公告)号：FR2829279B1

公开(公告)日：2003-12-12

申请号：FR0111381

申请日：2001-09-03

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  CASPAR DANIEL ,  FOURNEL RICHARD

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

公开(公告)号：FR2838256A1

公开(公告)日：2003-10-10

申请号：FR0204303

申请日：2002-04-08

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  LASSEUGUETTE JEAN ,  SCHOELLKOPF JEAN PIERRE

IPC: H03K19/00 ,  H03K3/012

Abstract: The component (C) comprises several complementary MOS transistors implemented or complementary substrates whereon the substrate potentials (VPWELL, VNWELL) are applied. The component (C) is put in waiting mode by decreasing the higher potential and increasing the lowre potential while the substrate potentials remain unchanged. The integrated circuit comprises the component (C), where the first potential of substrate (VDD0 or VSS0) is applied on a substrate of the first type component, and a potential limiter (R1) provides the component (C) as a substrate (VDD0 or VSS0), or the first limited potential (VDD1 or VSS1). The second potential of substrate (VSS0 or GND0) is applied to a substrate of the second type (p or n), and a potential limiter (R2) provides the supply potential (VSS or VDD), which is equal to the second potential of substrate (VSS0 or VDD0), or the second limited potential (VSS1 or VDD1). The potential limiter (R1) comprises a transistor (P0) whose source and substrate receive the first potential of substrate (VDD0), the gate receives a control signal (/REGUL) representative of the mode of functioning, and the first supply potential (VDD) is produced on the drain of the transistor; a transistor (N3) whose drain is connected to the source of the transistor (P0), and the source is connected to the gate by the intermediary of an inverter (11). The potential limiter (R2) comprises a transistor (N0) whose source and substrate receive the second potential of substrate (VSS0), the gate receives a control signal (REGUL), and the second supply potential (VSS) is produced on the drain of the transistor; and a transistor (P3) whose drain is connected to the source of the transistor (N0), and the source is connected to the gate by the intermediary of an inverter (I2).

公开(公告)号：FR2824413B1

公开(公告)日：2003-07-25

申请号：FR0106091

申请日：2001-05-07

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  FOURNEL RICHARD ,  THOMAS SIGRID

IPC: G11C16/04 ,  G11C16/02

Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the ouput signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

公开(公告)号：FR2826509A1

公开(公告)日：2002-12-27

申请号：FR0108427

申请日：2001-06-26

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  CANDELIER PHILIPPE ,  COLOMBET NORBERT

IPC: H01L23/367 ,  H01L23/525 ,  H01L23/552

Abstract: The multilayer semiconductor device (1) of integrated electronic components comprises at least one electrical connection strip constituting a strip-fuse (2) in at least one layer, laid out so that it can be severed and whose extremity is connected to at least one integrated electronic component (4), and intermediate elements (5) for electrical connection and thermal dissipation. The intermediate elements (5) comprise at least one electrical connection strip extending in the form of a streamer (11), which is connected to the strip-fuse (2), through the thermal dissipation elements (6). The device also comprises a thermal screen (13) which is electrically insulated and placed in the immediate neighborhood of the strip-fuse (2), between the strip-fuse and the integrated electronic component. The intermediate elements (5) comprise the thermal dissipation strips (7) extending in different layers and connected by feedthroughs (8), in particular in a direction parallel to the strip-fuse. The screen (13) extends between the strip-fuse (2) and the intermediate elements (5), and the intermediate elements extensions (9) cross the screen (13). The screen (13) comprises strips spaced one from another and extended in different layers, placed one above another and connected by feedthroughs (15); this strip-screen extends perpendicular to the strip-fuse (2). The device comprises at least one protection diode (16) connected to the intermediate elements for electrical connection. The strip-fuse (2) can be severed by a laser beam directed to the bottom of a cavity (18).

公开(公告)号：FR2807208A1

公开(公告)日：2001-10-05

申请号：FR0003983

申请日：2000-03-29

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  FOURNEL RICHARD ,  DUTARTRE DIDIER ,  RIBOT PASCAL ,  PAOLI MARYSE

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L21/8239

Abstract: Non-volatile memory semiconductor device comprises silicon based semiconductor substrate (SB) containing a source region (S) and a drain region (D), a control gate (GC) and a floating gate (GF). The floating gate extends between the source and drain regions formed in the substrate, and the control gate is situated above the floating gate and juts out with respect to source and drain regions. An Independent claim is included for the fabrication of the non-volatile memory semiconductor device.

公开(公告)号：FR2801419A1

公开(公告)日：2001-05-25

申请号：FR9914519

申请日：1999-11-18

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD

IPC: G11C7/12 ,  G11C16/24 ,  H01L21/00

Abstract: The device (1) for reading an integrated circuit memory comprises a differential amplifier (2) with data (MTX) and reference (REF) inputs provided by respective outputs of data and reference current-voltage converters (CIVD, CIVR), which are connected to the data and reference bit lines (BL, BLref), respectively, a reading current generator (3) for the provision of a reference current (IR) and a data current (ID), which is a fraction of the reference current, a circuit (4) for an asymmetric precharge for bringing the data input (MTX) of differential amplifier to a higher voltage level than that of the reference input (REF), so to latch the output (Out) in a determined state. A detection circuit (5) and a logic circuit (6) are for detecting if there is a sufficiently large voltage gap between the two inputs of differential amplifier, and the provision of control signal to asymmetric precharge circuit (4), in order to stop the precharge and let the device automatically pass to an estimation phase. In the estimation phase, if the memory cell (Cm) is programmed, the output remains unchanged; if the memory cell is blank or erased, the output is latched in the other state. The method for reading an integrated circuit memory includes a precharge phase for precharging the data bit line (BL), which comprises a memory cell (Cm) to be read, and the reference bit line (BLref), which comprises a reference cell (Cref), and an estimation phase established by the current generator (3), which provides the reference current (IR) for the reference bit line, and a fraction of it as the data current (ID) for the data bit line. The asymmetric precharge is carried out so that the precharge current in the data bit line is higher than that in the reference bit line, by the circuit (4) delivering a precharge current (Ipch). The asymmetric precharge circuit (4) and the current generator (3) are activated by the detection of a read control signal (SON), and the circuit (4) stops the precharging when the stop condition is met, which corresponds to the sufficiently large voltage gap. The read control signal (SON) is generated at the instant or after the selection of data and reference bit lines. The asymmetric precharge circuit (4) comprises a transistor (T8) for providing a supplementary precharge current to the bit line (BL) associated with the data input (MTX) of differential amplifier. Each current-voltage converter contains a transistor (Tp) connected between input and output nodes, and a feedback loop comprising an inverter (I1), for the control of gate voltage as a function of input node voltage. The logic circuit (6) provides the signal for activation of asymmetric precharge circuit as a function of stop control signal and the read control signal (SON). The logic circuit (6) contains a memory element of type latch RS. The differential amplifier comprises an output stage dimensioned so to favor the latching of output in opposite polarity to that of latching in the precharge phase, and a second output stage identical to the first and connected in the other branch. An integrated circuit memory comprises the proposed reading device.

公开(公告)号：DE69418976T2

公开(公告)日：1999-10-07

申请号：DE69418976

申请日：1994-11-08

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  FRUHAUF SERGE ,  TAILLET FRANCOIS

IPC: B42D15/10 ,  G06K19/07 ,  G06K19/077 ,  H01L21/82 ,  H01L27/02

Abstract: The invention relates to fuses for an integrated circuit. Such fuses are useful for irreversibly preventing access to certain regions of the integrated circuit. They serve particularly in applications for memory cards. According to the invention, a fuse is provided consisting of an NP junction of shallow depth (12, 11) covered by a metal contact (22), the semiconducting region covered over not being heavily doped. In order to blow the fuse, the junction is forward-biased with a current which is sufficient to allow diffusion of metal as far as the junction, which short-circuits it. Detection is carried out also by forward-biasing the junction, but with a low current or a low voltage. Detection can also be carried out in reverse bias.

公开(公告)号：DE60032864D1

公开(公告)日：2007-02-22

申请号：DE60032864

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD

IPC: G01R19/165 ,  G05F1/571 ,  G05F3/24 ,  G11C5/14 ,  G11C16/12

Abstract: A device for detecting the application of a high voltage signal to an internal node of an integrated circuit includes a high-voltage divider circuit and a threshold detection circuit. The threshold detection circuit receives a signal given by the output of the divider circuit, and provides a threshold crossing detection signal at an output thereof based upon the signal crossing a threshold. The detection circuit is connected between the logic supply voltage and ground, and further includes a negative feedback loop. The negative feedback loop is connected to the output of the divider circuit to limit the voltage build-up of the high voltage signal at the output thereof after the crossing of the detection threshold by the signal.

公开(公告)号：DE60301119T2

公开(公告)日：2006-06-01

申请号：DE60301119

申请日：2003-12-08

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

IPC: G11C17/14 ,  G11C14/00

Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.