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    33.
    发明专利
    未知

    公开(公告)号：IT1316870B1

    公开(公告)日：2003-05-12

    申请号：ITMI20000687

    申请日：2000-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  COMMODARO STEFANO ,  PICCA MASSIMILIANO ,  MONGELLI PATRIZIA

    IPC: G11C29/56

    Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.

    34.
    发明专利
    未知

    公开(公告)号：DE69426818T2

    公开(公告)日：2001-10-18

    申请号：DE69426818

    申请日：1994-06-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  CAMERLENGHI EMILIO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/50 ,  H01L27/00 ,  G06F11/20

    Abstract: Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.

    36.
    发明专利
    未知

    公开(公告)号：DE69514502D1

    公开(公告)日：2000-02-17

    申请号：DE69514502

    申请日：1995-05-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDARIDA LORENZO ,  CAMPARDO GIOVANNI ,  FUSILLO GIUSEPPE ,  SILVAGNI ANDREA

    IPC: G11C8/12 ,  G11C16/08 ,  G11C11/00 ,  G11C8/00

    Abstract: A memory array (2) is divided, at the design stage, into a plurality of elementary sectors (4); depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors (34) of desired size and number; a correlating unit (31) memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address (32) is supplied to the correlating unit (31) which provides for addressing the elementary sectors (4) associated with the addressed composite sector on the basis of the memorized correlation table.

    37.
    发明专利
    未知

    公开(公告)号：DE69325442T2

    公开(公告)日：1999-12-16

    申请号：DE69325442

    申请日：1993-03-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: To reduce the number of depleted cells (21) and the errors caused thereby, the memory array (20) comprises a number of groups of control transistors (23) relative to respective groups (22) of memory cells. The control transistors (23) of each group are NMOS transistors having the drain terminal connected to its own control line (BLP), and each of the control transistors of one group is relative to a row portion of the memory array (20): More specifically, each control transistor (23) presents the control gate connected to the respective word line (WL), and the source region connected to the source region of the cells (21) in the same row and in the same group (22).

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