公开(公告)号：EP0697739B1

公开(公告)日：2001-10-31

申请号：EP94830393.8

申请日：1994-08-02

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Ferla, Giuseppe ,  Frisina, Ferruccio

IPC: H01L29/739

CPC classification number: H01L29/7395

公开(公告)号：EP1014565A1

公开(公告)日：2000-06-28

申请号：EP98830772.4

申请日：1998-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Palmisano, Giuseppe ,  Ferla, Giuseppe ,  Girlando, Giovanni

IPC: H03F1/56 ,  H03F1/22

CPC classification number: H03F1/22 ,  H03F1/565 ,  H03F2200/294 ,  H03F2200/372

Abstract: The amplifier stage (50) comprises a first (2) and a second (3) transistor, connected in series to each other between a first (4) and a second (5) reference potential line. The first transistor (2) has a control terminal (10), connected to an input (11) of the amplifier stage (50) through a first inductor (12), a first terminal (15), connected to the second reference potential line (5) through a second inductor (16), and a third terminal (17) connected to a first terminal of the second transistor (3). The second transistor has a second terminal (21) forming an output of the amplifier stage (50), and connected to the first reference potential line (4) through a load resistor (22). To improve the noise figure, a matching capacitor (51) is connected between the control terminal (10) and the first terminal (15) of the first transistor (2).

Abstract translation: 放大器级（50）包括在第一（4）和第二（5）参考电位线之间彼此串联连接的第一（2）和第二（3）晶体管。 第一晶体管（2）具有通过第一电感器（12）连接到放大器级（50）的输入端（11）的控制端子（10），连接到第二参考电位线的第一端子（15） （5）通过第二电感器（16）和连接到第二晶体管（3）的第一端子的第三端子（17）。 第二晶体管具有形成放大级（50）的输出的第二端（21），并通过负载电阻（22）连接到第一参考电位线（4）。 为了提高噪声系数，在控制端子（10）和第一晶体管（2）的第一端子（15）之间连接有匹配电容器（51）。

公开(公告)号：EP0993033A1

公开(公告)日：2000-04-12

申请号：EP98830585.0

申请日：1998-10-06

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio ,  Ferla, Giuseppe

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7802 ,  G11C29/14 ,  G11C29/50 ,  G11C2029/0403 ,  H01L21/76202 ,  H01L21/8238 ,  H01L29/6656 ,  H01L29/66712

Abstract: Semiconductor power device comprising a semiconductor layer (1) of a first type of conductivity, wherein a body region (2) of a second type of conductivity comprising source regions (3) of the first type of conductivity is formed, a gate oxide layer (4) superimposed to the semiconductor layer (1) with an opening over the body region (2), polysilicon regions (5) superimposed to the gate oxide layer (4), and regions of a first insulating material (6) superimposed to the polysilicon regions (5). The device comprises regions of a second insulating material (10) situated on side of both the polysilicon regions (5) and the regions of a first insulating material (6) and over zones (14) of the gate oxide layer (4) situated near the opening on the body region (2), oxide regions (9) interposed between the polysilicon regions (5) and the regions of a second insulating material (10), oxide spacers (8) superimposed to the regions of a second insulating material (10).

Abstract translation: 半导体功率器件包括第一导电类型的半导体层（1），其中形成第一导电类型的源区（3）的第二导电类型的体区（2），栅极氧化层 4），叠加到所述体区（2）上的开口叠加到所述半导体层（1），叠加到所述栅极氧化物层（4）的多晶硅区域（5）和与所述多晶硅层叠叠的第一绝缘材料（6）的区域 地区（5）。 该器件包括位于两个多晶硅区域（5）和第一绝缘材料（6）的区域以及位于栅极氧化物层（4）附近的区域（14）的侧面上的第二绝缘材料（10）的区域 在体区域（2）上的开口，插入在多晶硅区域（5）和第二绝缘材料（10）的区域之间的氧化物区域（9），叠加到第二绝缘材料区域的氧化物间隔物（8） 10）。

公开(公告)号：EP1659636B1

公开(公告)日：2009-11-04

申请号：EP05025285.7

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Ferruccio, Frisina ,  Ferla, Giuseppe ,  Magri', Angelo ,  Grimaldi, Antonio Giuseppe ,  Bazzano, Gaetano

IPC: H01L29/78 ,  H01L29/49

CPC classification number: H01L29/7802 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4983

Abstract: Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors (2) and a gate structure (12) comprising a plurality of conductive strips (8) realised with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks (11) connected to a gate pad (30) and at least a connection layer (20) arranged in series to at least one of said conductive strip (8). Such gate structure (12) comprising at least a plurality of independent islands (10) formed on the upper surface (9) of the conductive strips (8) and suitably formed on the connection layers (20). Said islands (10) being realised with at least one second conductive material such as silicide.

公开(公告)号：EP1408542A3

公开(公告)日：2009-01-21

申请号：EP03025806.5

申请日：1994-07-14

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Ferla, Giuseppe ,  Frisinam Ferruccio

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/74 ,  H01L29/49 ,  H01L29/739

CPC classification number: H01L29/7802 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high-speed MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a lightly doped semiconductor layer (1) of a first conductivity type, the elementary functional units comprising channel regions (6) of a second conductivity type covered by a conductive insulated gate layer (8) comprising a polysilicon layer (5); the conductive insulated gate layer (8) also comprises a highly conductive layer (9) superimposed over said polysilicon (5) layer and having a resistivity much lower than the resistivity of the polysilicon layer (5), so that a resistance introduced by the polysilicon layer (5) is shunted with a resistance introduced by said highly conductive layer (9) and the overall resistivity of the conductive insulated gate (8) layer is lowered.

公开(公告)号：EP1659637A3

公开(公告)日：2006-07-19

申请号：EP05025287.3

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Arena, Giuseppe ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

Abstract: The invention relates to a process for the realisation of a high integration density power MOS device comprising the following steps of:

providing a doped semiconductor substrate (10) with a first type of conductivity (N);
forming, on the substrate (10), a semiconductor layer (11) with lower conductivity (N-);
forming, on the semiconductor layer (11), a dielectric layer (16) of thickness comprised between 3000 and 13000 A (Angstrom);
depositing, on the dielectric layer (16), a hard mask layer;
masking the hard mask layer by means of a masking layer;
etching the hard mask layers and the underlying dielectric layer (16) for defining a plurality of hard mask portions (19) to protect said dielectric layer (16);
removing the masking layer;
isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer (16) below said hard mask portions (19);
forming a gate oxide (15) of thickness comprised between 150 and 1500 A (Angstrom)
depositing a conductor material (24) in said cavities and above the same to form a recess spacer (20), which is totally aligned with a gate structure (14) comprising said thick dielectric layer (16) and said gate oxide (15).

公开(公告)号：EP1455397A2

公开(公告)日：2004-09-08

申请号：EP03029916.8

申请日：2003-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Magri', Angelo ,  Frisina, Feruccio ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66712

Abstract: The invention relates to a vertical-conduction and planar-structure MOS device having a double thickness of gate oxide comprising

a first portion (5a) of gate oxide having a lower thickness in a channel area close to the active areas (4), and a second portion (5b) of thicker gate oxide in a central area (11) on a JFET area and
an enrichment region (9) in the JFET area under the second . portion (5b) of thicker gate oxide (11).

The invention also relates to a method for realising on a semiconductor substrate (2) MOS transistor electronic devices (1) with improved static and dynamic performances and high scaling down density, these transistors having traditional active areas (4) defined in the substrate (2) at the periphery of a channel region whereon a gate region is realised. The method provides at least the following steps:

realising the MOS transistor starting from a planar structure with a double thickness of gate oxide comprising a thin layer in the channel area close to the active areas (4) and a thicker layer in the central area (11) on the channel; and
realising an enrichment region (9) in the JFET area below the thicker layer.

Abstract translation: 本发明涉及一种垂直导电和平面结构MOS器件，其具有栅极氧化物的双重厚度，其包括在接近有源区（4）的沟道区中具有较低厚度的栅极氧化物的第一部分（5a） 在JFET区域上的中心区域（11）中较厚的栅极氧化物的第二部分（5b）和第二部分的JFET区域中的富集区域（9）。 较厚栅极氧化物（11）的部分（5b）。 本发明还涉及一种在具有改进的静态和动态性能以及高缩小密度的半导体衬底（2）MOS晶体管电子器件（1）上实现的方法，这些晶体管具有传统的有源区域（4） 在实现栅极区域的沟道区域的周围的衬底（2）。 该方法至少提供以下步骤：从具有双重厚度的栅极氧化物的平面结构开始实现MOS晶体管，该栅极氧化物在靠近有源区域（4）的沟道区域中具有薄层，并且在中心区域中具有较厚层（ 11）在频道上 并且在较厚层下面的JFET区域中实现富集区域（9）。

公开(公告)号：EP1278234A3

公开(公告)日：2004-04-28

申请号：EP01127923.9

申请日：2001-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Cerofolini, Gianfranco ,  Ferla, Giuseppe

IPC: H01L21/28 ,  H01L29/51 ,  H01L51/20

CPC classification number: H01L21/28167 ,  H01L29/51

Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer (3) formed between two silicon plates (1,2), and wherein the silicon plates (1,2) overhang the oxide layer (3) all around to define an undercut (5) having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates (1,2) to have different functional groups (6,7) provided in the undercut (5) from those in the remainder of the surfaces; and selectively reacting the functional groups (6,7) provided in the undercut (5) with an organic molecule (8) having a reversibly reducible center and a molecular length substantially equal to the width of the undercut (5), thereby to establish a covalent bond to each end of the organic molecule (8).

公开(公告)号：EP1058315A1

公开(公告)日：2000-12-06

申请号：EP99830340.8

申请日：1999-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Grimaldi, Antonio ,  Schillaci, Antonino ,  Ferla, Giuseppe

IPC: H01L29/06 ,  H01L29/41

CPC classification number: H01L29/404 ,  H01L27/0629

Abstract: Semiconductor device for high voltages comprising at least one power component (21) and at least one edge termination (100). Said edge termination (100) comprises a voltage divider including a plurality of capacitors (C7, C8, C9, C10, C11, C12) in series, which are formed by couples of said capacitors (C7, C8, C9, C10, C11, C12) formed by metal layers (71; 72) of a first level and polysilicon layers (11) of a second level interposed from a dielectric layer (8) underlying said metal layers (71; 72). The metal layers (71; 72) are alternated to said polysilicon layers (11) but extend in part over a zone of said dielectric layer (8) superimposed on said polysilicon layers (11). The edge termination (100) is connected between non-driveable terminals of said power component (21).

Abstract translation: 用于高电压的半导体器件包括至少一个功率部件（21）和至少一个边缘终端（100）。 所述边缘终端（100）包括分压器，其包括串联的多个电容器（C7，C8，C9，C10，C11，C12），所述电容器由所述电容器（C7，C8，C9，C10，C11， 由第一级的金属层（71; 72）形成的第二层的第二层（11）和从第一层的介电层（8）介入的第二层的多晶硅层（11）形成。 金属层（71; 72）与所述多晶硅层（11）交替，但部分地跨越叠加在所述多晶硅层（11）上的所述介电层（8）的区域。 边缘终端（100）连接在所述功率部件（21）的不可驱动端子之间。